PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 139

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PIC18F6621-I/PT

Manufacturer Part Number
PIC18F6621-I/PT
Description
64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F6621-I/PT

A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
54
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
3.8K Bytes
Speed
40 MHz
Timers
2-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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12.2
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low-power oscillator rated up to 200 kHz. It will
continue to run during Sleep. It is primarily intended for
a 32 kHz crystal. The circuit for a typical LP oscillator is
shown in Figure 12-3. Table 12-1 shows the capacitor
selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
TABLE 12-1:
 2005 Microchip Technology Inc.
Osc Type
Note:
Note 1: Microchip suggests 33 pF as a starting
LP
2: Higher capacitance increases the stability
3: Since each resonator/crystal has its own
4: Capacitor values are for design guidance
Timer1 Oscillator
33 pF
33 pF
C1
C2
See the notes with Table 12-1 for additional
information about capacitor selection.
point in validating the oscillator circuit.
of the oscillator but also increases the
start-up time.
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
components.
only.
32 kHz
32.768 kHz
XTAL
Freq
CAPACITOR SELECTION
FOR THE ALTERNATE
OSCILLATOR
Crystal Tested
32.768 kHz
EXTERNAL COMPONENTS
FOR THE TIMER1
LP OSCILLATOR
15-22 pF
values
T1OSI
T1OSO
PIC18F6X2X/8X2X
C1
(2-4)
(1)
of
15-22 pF
PIC18F6525/6621/8525/8621
external
C2
(1)
12.3
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing the TMR1 Interrupt Enable bit, TMR1IE
(PIE1<0>).
12.4
If either the ECCP1 or ECCP2 module is configured in
Compare mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1. The trigger for ECCP2 will also start an A/D
conversion if the A/D module is enabled.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from ECCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
12.5
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, is valid due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
Note:
Timer1 Interrupt
Resetting Timer1 Using an ECCP
Special Trigger Output
Timer1 16-Bit Read/Write Mode
The special event triggers from the
ECCP1 module will not set interrupt flag
bit TMR1IF (PIR1<0>).
DS39612B-page 137

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