PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 76

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
6.2.2
Figure 6-2 shows an example of 16-bit Word Write
mode for PIC18F8525/8621 devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of word-
wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
During
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is tri-
stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 6-2:
DS39612B-page 74
a
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
16-BIT WORD WRITE MODE
PIC18F8X2X
TBLWT
AD<15:8>
A<19:16>
AD<7:0>
cycle
16-BIT WORD WRITE MODE EXAMPLE
WRH
ALE
CE
OE
to
an
even
address
373
373
During
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
A<20:1>
D<15:0>
a
TBLWT
Address Bus
Data Bus
Control Lines
D<15:0>
A<x:0>
cycle
 2005 Microchip Technology Inc.
CE
EPROM Memory
to
OE
JEDEC Word
an
WR
odd
(1)
address