PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 295

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2005 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
=
=
>
=
≤
=
register ‘f’
operation
operation
operation
Compare f with W, Skip if f > W
[ label ] CPFSGT
0 ≤ f ≤ 255
a ∈ [0,1]
(f) − (W);
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note:
HERE
NGREATER
GREATER
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
3 cycles if skip and followed
by a 2-word instruction.
010a
operation
operation
operation
CPFSGT REG, 0
:
:
Process
Data
No
No
No
Q3
Q3
Q3
f [,a]
ffff
operation
operation
operation
operation
PIC18F6525/6621/8525/8621
No
No
No
No
Q4
Q4
Q4
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
If REG
Q1
Q1
Q1
PC
PC
=
=
<
=
≥
=
register ‘f’
operation
operation
operation
Compare f with W, Skip if f < W
[ label ] CPFSLT
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W);
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
1
1(2)
Note:
HERE
NLESS
LESS
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
3 cycles if skip and followed
by a 2-word instruction.
CPFSLT REG, 1
:
:
000a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39612B-page 293
f [,a]
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff