PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 153

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.2
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 regis-
ters when an event occurs on pin RG3/CCP4/P1D. An
event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP4M3:CCP4M0
capture is made, the interrupt request flag bit CCP4IF
(PIR3<1>) is set; it must be cleared in software. If
another capture occurs before the value in register
CCPR4 is read, the old captured value is overwritten by
the new captured value.
16.2.1
In Capture mode, the RG3/CCP4/P1D pin should be
configured as an input by setting the TRISG<3> bit.
16.2.2
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the T3CON register (see Section 16.1.1 “CCP
Modules and Timer Resources”).
FIGURE 16-2:
 2005 Microchip Technology Inc.
Note:
Capture Mode
RG3/CCP4/P1D pin
CCP PIN CONFIGURATION
If the RG3/CCP4/P1D is configured as an
output, a write to the port can cause a
capture condition.
TIMER1/TIMER3 MODE SELECTION
(CCP4CON<3:0>).
CAPTURE MODE OPERATION BLOCK DIAGRAM
Q’s
Edge Detect
Prescaler
÷ 1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP4IF
When
PIC18F6525/6621/8525/8621
a
T3CCP2
T3CCP2
16.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP4IE (PIE3<1>) clear to avoid false interrupts and
should clear the flag bit, CCP4IF, following any such
change in operating mode.
16.2.4
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP4M3:CCP4M0). Whenever
the CCP module is turned off or the CCP module is not
in Capture mode, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 16-1:
CLRF
MOVLW
MOVWF
CCP4CON
NEW_CAPT_PS ; Load WREG with the
CCP4CON
SOFTWARE INTERRUPT
CCP PRESCALER
TMR1
Enable
TMR3
Enable
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
CCPR4H
TMR1H
TMR3H
CCPR4L
DS39612B-page 151
TMR3L
TMR1L