PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 165

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 17-3:
17.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin
(Figure 17-4). This mode can be used for half-bridge
applications, as shown in Figure 17-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 17.4.6
“Programmable Dead-Band Delay” for more details
on dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
 2005 Microchip Technology Inc.
Relationships:
• Period = 4 * T
• Duty Cycle = T
• Delay = 4 * T
Note 1:
00
10
01
11
HALF-BRIDGE MODE
(Single Output)
CCP1CON
(Half-Bridge)
(Full-Bridge,
(Full-Bridge,
Reverse)
Forward)
<7:6>
Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable
Dead-Band Delay”).
OSC
OSC
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
OSC
* (ECCP1DEL<6:0>)
* (PR2 + 1) * (TMR2 Prescale Value)
* (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
SIGNAL
PIC18F6525/6621/8525/8621
0
Delay
(1)
FIGURE 17-4:
P1A
P1B
Note 1: At this time, the TMR2 register is equal to the
Cycle
td = Dead Band Delay
Duty
(2)
(2)
2: Output signals are shown as active-high.
(1)
PR2 register.
td
Duty Cycle
Delay
Period
Period
(1)
td
HALF-BRIDGE PWM
OUTPUT
(1)
DS39612B-page 163
Period
PR2 + 1
(1)