PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 151

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.0
PIC18F6525/6621/8525/8621 devices all have a total
of five CCP (Capture/Compare/PWM) modules. Two of
these (CCP4 and CCP5) implement standard Capture,
Compare and Pulse-Width Modulation (PWM) modes
and are discussed in this section. The other three
modules
standard Capture and Compare modes, as well as
Enhanced PWM modes. These are discussed in
Section 17.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
REGISTER 16-1:
 2005 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
(ECCP1,
bit 7-6
bit 5-4
bit 3-0
ECCP2,
CCPxCON REGISTER (CCP4 AND CCP5 MODULES)
bit 7
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The
eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode; initialize CCP pin low; on compare match, force CCP pin high
1001 = Compare mode; initialize CCP pin high; on compare match, force CCP pin low
1010 = Compare mode; generate software interrupt on compare match (CCPIF bit is set,
1011 = Reserved
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
U-0
—
(CCPIF bit is set)
CCP pin reflects I/O state)
(CCPIF bit is set)
ECCP3)
U-0
—
implement
PIC18F6525/6621/8525/8621
DCxB1
R/W-0
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules. The operations of PWM mode described in
Section 16.4 “PWM Mode” apply to CCP4 and CCP5
only.
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCPxM3
R/W-0
Throughout this section and Section 17.0
“Enhanced
(ECCP) Module”, references to register
and bit names that may be associated with
a specific CCP module are referred to
generically by the use of ‘x’ or ‘y’ in place of
the
“CCPxCON” might refer to the control
register for CCP4 or CCP5, or ECCP1,
ECCP2 or ECCP3. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of
whether the CCP module is a standard or
Enhanced implementation.
specific
CCPxM2 CCPxM1 CCPxM0
R/W-0
module
Capture/Compare/PWM
x = Bit is unknown
R/W-0
DS39612B-page 149
number.
R/W-0
Thus,
bit 0