PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 56

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
TABLE 4-3:
DS39612B-page 54
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
ECCP1DEL
TMR4
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
Legend:
Note
File Name
(3)
1:
2:
3:
4:
5:
(3)
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other
oscillator modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6525/6621 devices and read as ‘0’.
RG5 is available only if MCLR function is disabled in configuration.
Enabled only in Microcontroller mode for
Enhanced USART1 Baud Rate Generator Register High Byte
Enhanced USART2 Baud Rate Generator Register High Byte
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 4 Low Byte
Capture/Compare/PWM Register 5 High Byte
Capture/Compare/PWM Register 5 Low Byte
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
Timer4 Register
Timer4 Period Register
Enhanced USART2 Baud Rate Generator Register Low Byte
Enhanced USART2 Receive Register
Enhanced USART2 Transmit Register
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
P1RSEN
P3RSEN
P2RSEN
CSRC
SPEN
Bit 7
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON
P1DC6
P3DC6
P2DC6
RCIDL
RCIDL
RA6
Bit 6
RX9
TX9
—
—
—
(1)
Read PORTA pins, Write PORTA Data Latch
P1DC5
DC4B1
DC5B1
P3DC5
P2DC5
RG5
SREN
TXEN
Bit 5
—
—
(4)
Read PORTG pins, Write PORTG Data Latch
P1DC4
DC4B0
DC5B0
P3DC4
P2DC4
SCKP
SCKP
SYNC
CREN
PIC18F8525/8621 devices.
Bit 4
PSS3AC1
PSS2AC1
CCP4M3
CCP5M3
SENDB
ADDEN
BRG16
BRG16
P1DC3
P3DC3
P2DC3
Bit 3
PSS3AC0
PSS2AC0
CCP4M2
CCP5M2
P1DC2
P3DC2
P2DC2
BRGH
FERR
Bit 2
(1)
—
—
T4CKPS1
PSS3BD1
PSS2BD1
CCP4M1
CCP5M1
P1DC1
P3DC1
P2DC1
TRMT
OERR
WUE
WUE
Bit 1
 2005 Microchip Technology Inc.
T4CKPS0 -000 0000
PSS3BD0 0000 0000
PSS2BD0 0000 0000
CCP4M0
CCP5M0
ABDEN
ABDEN
P1DC0
P3DC0
P2DC0
RX9D
TX9D
Bit 0
xxxx xxxx
0000 xxxx
--xx xxxx
x000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000
0000 0000
-1-0 0-00
0000 0000
-1-0 0-00
0000 0000
0000 0000
1111 1111
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
POR, BOR
Value on
on page:
35, 127
35, 124
36, 121
36, 119
36, 116
36, 113
36, 110
36, 108
36, 105
36, 217
36, 216
36, 217
36, 216
36, 168
36, 148
36, 148
36, 147
36, 153
36, 153
36, 149
36, 153
36, 153
36, 149
36, 217
36, 224
36, 222
36, 222
36, 222
36, 169
36, 168
36, 169
36, 168
Details