PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 297

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2005 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
If CNT
Q1
Q1
Q1
PC
PC
=
=
=
=
≠
=
register ‘f’
operation
operation
operation
Decrement f, Skip if 0
[ label ] DECFSZ f [,d [,a]]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – 1 → dest;
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
No
No
No
0010
Q2
Q2
Q2
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
by a 2-word instruction.
11da
operation
operation
operation
GOTO
DECFSZ
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT, 1, 1
LOOP
destination
operation
operation
operation
Write to
PIC18F6525/6621/8525/8621
No
No
No
Q4
Q4
Q4
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Decrement f, Skip if Not 0
[ label ] DCFSNZ
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – 1 → dest;
skip if result ≠ 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
=
=
=
=
≠
=
3 cycles if skip and followed
by a 2-word instruction.
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
DCFSNZ
:
:
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39612B-page 295
f [,d [,a]
ffff
TEMP, 1, 0
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff