PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 240

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
20.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (R
switch (R
required to charge the capacitor C
switch (R
(V
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
EQUATION 20-1:
EQUATION 20-2:
EQUATION 20-3:
DS39612B-page 238
T
V
or
Tc
T
Temperature coefficient is only required for temperatures > 25°C.
T
T
T
ACQ
ACQ
ACQ
C
ACQ
DD
Note:
HOLD
). The source impedance affects the offset voltage
A/D Acquisition Requirements
SS
=
=
=
=
=
=
SS
=
=
) impedance varies over the device voltage
When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
) impedance directly affect the time
T
2 µs + T
-C
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
T
(V
-(120 pF)(1 kΩ + R
AMP
AMP
REF
HOLD
+ T
+ T
– (V
ACQUISITION TIME
A/D MINIMUM CHARGING TIME
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
C
S
(R
C
) and the internal sampling
C
+ [(Temp – 25°C)(0.05 µs/°C)]
IC
REF
+ T
+ T
+ R
/2048)) • (1 – e
COFF
COFF
SS
HOLD
SS
+ R
HOLD
+ R
) must be allowed
S
) ln(1/2047)
S
. The sampling
) ln(1/2047)
(-Tc/C
HOLD
(R
IC
+ R
SS
+ R
S
))
To
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 20-3 shows the calculation of the minimum
required acquisition time, T
based
assumptions:
C
Rs
Conversion Error
V
Temperature
V
)
DD
HOLD
HOLD
calculate
on
the
the
=
=
≤
=
=
=
following
minimum
 2005 Microchip Technology Inc.
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
ACQ
. This calculation is
application
acquisition
system
time,