PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 219

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.1
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the
period of a free running timer. In Asynchronous mode,
bits BRGH (TXSTAx<2>) and BRG16 also control the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 19-1 shows the formula for computation of the
baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 19-1. From
TABLE 19-1:
EXAMPLE 19-1:
TABLE 19-2:
 2005 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair
TXSTAx
RCSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
For a device with F
Desired Baud Rate = F
Solving for SPBRGHx:SPBRGx:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Name
SYNC
0
0
0
0
1
1
X
EUSART Baud Rate Generator
(BRG)
=
=
=
=
=
=
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Configuration Bits
Enhanced USARTx Baud Rate Generator Register High Byte
Enhanced USARTx Baud Rate Generator Register Low Byte
CSRC
SPEN
Bit 7
((F
((16000000/9600)/64) – 1
[25.042] = 25
9615
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
—
BAUD RATE FORMULAS
BRG16
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
OSC
OSC
0
0
1
1
0
1
/Desired Baud Rate)/64) – 1
CALCULATING BAUD RATE ERROR
OSC
RCIDL
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Bit 6
TX9
RX9
/(64 ([SPBRGHx:SPBRGx] + 1))
SREN
TXEN
BRGH
Bit 5
—
0
1
0
1
x
x
OSC
, the nearest
SYNC
CREN
SCKP
Bit 4
PIC18F6525/6621/8525/8621
SENDB
ADDEN
BRG16
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
Bit 3
8-bit/Synchronous
BRGH
FERR
Bit 2
this, the error in baud rate can be determined. An
example calculation is shown in Example 19-1. Typical
baud rates and error values for the various Asynchro-
nous modes are shown in Table 19-2. It may be
advantageous to use the high baud rate (BRGH = 1) or
the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGHx:SPBRGx regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
19.1.1
The data on the RXx pin (either RC7/RX1/DT1 or RG2/
RX2/DT2) is sampled three times by a majority detect
circuit to determine if a high or a low level is present at
the RXx pin.
—
OERR
TRMT
WUE
Bit 1
SAMPLING
ABDEN
RX9D
TX9D
Bit 0
Baud Rate Formula
0000 0010
0000 000x
-1-0 0-00
0000 0000
0000 0000
POR, BOR
F
F
Value on
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39612B-page 217
other Resets
Value on all
0000 0010
0000 000x
-1-0 0-00
0000 0000
0000 0000