PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 143

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.0
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• MSSP module optional use of TMR2 output to
Timer2 has a control register shown in Register 13-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>)
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control
register. The prescaler and postscaler selection of
Timer2 are controlled by this register.
REGISTER 13-1:
 2005 Microchip Technology Inc.
generate clock shift
TIMER2 MODULE
bit 7
bit 6-3
bit 2
bit 1-0
to
minimize
bit 7
Unimplemented: Read as ‘0’
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
T2CON: TIMER2 CONTROL REGISTER
Legend:
R = Readable bit
-n = Value at POR
U-0
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
power
R/W-0
consumption.
PIC18F6525/6621/8525/8621
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
13.1
Timer2 can be used as the PWM time base for the
PWM mode of the ECCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (F
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0
output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt, latched in flag bit TMR2IF (PIR1<1>).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
TMR2 is not cleared when T2CON is written.
Watchdog Timer Reset, or Brown-out Reset)
Timer2 Operation
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
(T2CON<1:0>).
OSC
/4) has a prescale option
x = Bit is unknown
R/W-0
DS39612B-page 141
The
R/W-0
match
bit 0