PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 78

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
6.2.4
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
FIGURE 6-5:
DS39612B-page 76
AD<15:0>
A<19:16>
Instruction
Execution
AD<15:0>
A<19:16>
Memory
Cycle
Instruction
Execution
ALE
Memory
CE
OE
WRH
Apparent Q
WRL
Cycle
16-BIT MODE TIMING
BA0
ALE
OE
CE
Actual Q
‘1’
‘0’
‘1’
Q1
EXTERNAL MEMORY BUS TIMING FOR TBLRD
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
(EXTENDED MICROCONTROLLER MODE)
Opcode Fetch
INST(PC – 2)
from 000100h
Q1
Q1
Q2
TBLRD*
3AABh
TBLRD Cycle 1
Opcode Fetch
from 007556h
Q2
Q2
Q3
MOVLW 55h
00h
Q4
Q3
Q3
0E55h
Q1
Q4
Q4
TBLRD Cycle 1
Opcode Fetch
from 000102h
MOVLW 55h
Q2
Q1
Q1
Q3
CF33h
Q2
Q2
Q4
Q3
Q3
Q1
TBLRD Cycle 2
from 199E67h
CF33h
Table Read
from 199E67h
TBLRD Cycle 2
TBLRD 92h
of 92h
Q2
Q4
Q4
0Ch
0Ch
Q3
Q4
Q1
9256h
9256h
Q4
Q4
Q2
1 T
 2005 Microchip Technology Inc.
Q1
CY
Wait
Opcode Fetch
from 000104h
Q4
Q3
ADDLW 55h
Q2
MOVLW
Q4
Q4
Q3
‘1’
‘1’
‘0’
Q4