DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet
DS33R11+
Specifications of DS33R11+
Related parts for DS33R11+
DS33R11+ Summary of contents
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GENERAL DESCRIPTION The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream. The device performs store-and-forward of packets with full wire-speed transport capability. The built-in ...
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DESCRIPTION ................................................................................................................................... 9 2 FEATURE HIGHLIGHTS.................................................................................................................. 11 2.1 G ...................................................................................................................................... 11 ENERAL 2 ICROPROCESSOR NTERFACE 2.3 HDLC E M THERNET APPING 2.4 X. INK CCESS 2.5 A HDLC C DDITIONAL ONTROLLERS IN THE 2.6 ...
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DTE and DCE Mode .............................................................................................................................58 9.15 E MAC ........................................................................................................................... 59 THERNET 9.15.1 MII Mode Options..................................................................................................................................61 9.15.2 RMII Mode.............................................................................................................................................61 9.15.3 PHY MII Management Block and MDIO Interface ................................................................................62 9.16 BERT E IN THE THERNET 9.16.1 Receive Data Interface .........................................................................................................................63 9.16.2 ...
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FIFO Information ...................................................................................................................................96 10.17.5 Receive Packet-Bytes Available ...........................................................................................................96 10.18 L FDL S EGACY UPPORT 10.18.1 Overview ...............................................................................................................................................97 10.18.2 Receive Section ....................................................................................................................................97 10.18.3 Transmit Section ...................................................................................................................................98 10.19 D4/SLC-96 O PERATION 10. ROGRAMMABLE N 10. ...
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E1 M .................................................................................................................................... 308 ODE 13 OPERATING PARAMETERS ........................................................................................................ 313 13 HERMAL HARACTERISTICS 13.2 MII I ............................................................................................................................ 315 NTERFACE 13.3 RMII I ......................................................................................................................... 317 NTERFACE 13.4 MDIO I ....................................................................................................................... 319 NTERFACE 13.5 T WAN I RANSMIT NTERFACE ...
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Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17 Figure 6-1. Main Block Diagram ................................................................................................................................ 20 Figure 6-2. Block Diagram of T1/E1/J1 Transceiver ................................................................................................. 21 Figure 6-3. Receive and Transmit T1/E1/J1 LIU ....................................................................................................... 22 Figure 6-4. Receive and Transmit ...
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Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................ 307 Figure 12-20. Receive-Side Timing ......................................................................................................................... 308 Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) .......................................................... 308 Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled)................................... 309 Figure 12-23. ...
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Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16 Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 25 Table 9-1. Clocking Options for the Ethernet Interface ............................................................................................. 43 Table 9-2. Reset Functions........................................................................................................................................ 46 Table 9-3. Registers Related to Connections and Queues ....................................................................................... 52 Table ...
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DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM ...
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The integrated Ethernet Mapper is software compatible with the DS33Z11 Ethernet mapper. There are a few things to note when porting a DS33Z11 application to this device: • The SPI and hardware modes are not supported. • RSER has been ...
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FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver source code, and ...
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Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Two additional independent HDLC controllers • Fast load and unload features for FIFOs • SS7 support for FISU transmit and receive • Independent 128-byte Rx and Tx buffers with interrupt ...
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T1/E1/J1 Line Interface • Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation • Fully software configurable • Short-haul and long-haul applications • Automatic receive sensitivity adjustments ...
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T1/E1/J1 Framer • Fully independent transmit and receive functionality • Full receive and transmit path transparency • T1 framing formats include D4 (SLC-96) and ESF • Detailed alarm and status reporting with optional interrupt support • Large path and ...
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Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit error-rate tester (BERT) • Pseudorandom patterns including QRSS • User-defined repetitive patterns • Daly pattern • Error insertion single and continuous • Total bit and errored bit counts ...
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Specifications Compliance The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11. Table 2-1. T1-Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications. RFC1662—PPP in HDLC-like ...
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APPLICATIONS The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4. For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Ethernet ...
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ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interface • FCS: Frame Check Sequence • HDLC: High-Level Data Link Control • MAC: Media Access Control • MII: Media Independent Interface ...
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MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation. ...
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BLOCK DIAGRAMS Figure 6-1. Main Block Diagram CLAD TTIP MUX TRING BERT RTIP MUX RRING JTAG2 NOTE: SOME PINS NOT SHOWN. THE BLOCK IN THE DIAGRAM LABELED “T1/E1/J1 TRANSCEIVER” IS DIVIDED INTO THREE FUNCTIONAL BLOCKS: LIU, FRAMER, AND BACKPLANE ...
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Figure 6-2. Block Diagram of T1/E1/J1 Transceiver CLOCK EXTERNAL ACCESS CLOCK TO RECEIVE SIGNALS ADAPTER RX LIU TX LIU LIU EXTERNAL ACCESS TO TRANSMIT SIGNALS HDB3 / B8ZS SYNC MUX SINGALING ALARM DET HDLCs FRAMER SINGALING ALARM GEN MUX HDLCs ...
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Figure 6-3. Receive and Transmit T1/E1/J1 LIU 32.768MHz RRING RTIP TRING TTIP VCO / PLL MUX 22 of 344 RCL MUX JACLK RPOS RCLK RNEG TNEG TCLK TPOS INTERNAL SIGNALS TO FRAMER ...
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Figure 6-4. Receive and Transmit T1/E1/J1 Framer RPOS RNEG RCLK TPOS TNEG TCLK INTERNAL SIGNALS FROM LIU REC HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte ...
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Figure 6-5. T1/E1/J1 Backplane Interface DATA CLOCK SYNC INTERNAL SIGNALS FROM FRAMER SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK MUX 24 of 344 RLINK RLCLK ...
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PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. LEGEND input output, Ipu = input with pullup, ...
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NAME PIN TYPE RD/DS B11 CS A11 CST D7 INT A10 OZ Read Data Strobe (Intel Mode): The DS33R11 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low. I Data ...
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NAME PIN TYPE COL_DET N18 RX_CRS/ M19 CRS_DV RX_CLK M20 RXD[0] L18 RXD[1] L19 RXD[2] L20 RXD[3] M18 RX_DV K19 RX_ERR K18 TX_CLK H19 DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver MII/RMII PHY PORT Collision Detect (MII): Asserted by the ...
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NAME PIN TXD[0] F19 TXD[1] F18 TXD[2] E20 TXD[3] E19 TX_EN F20 REF_CLK A19 REF_CLKO A20 DCEDTES G20 RMIIMIIS G19 TYPE Transmit Data 0 through 3(MII): TXD [3:0] is presented synchronously with the rising edge of TX_CLK. TXD [0] is ...
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NAME PIN TYPE MDC C19 MDIO C20 SCAS W7 SRAS W9 SDCS V10 SWE W10 SBA[0] Y11 SBA[1] V11 PHY MANAGEMENT BUS Management Data Clock (MII): Clocks management data between the PHY and DS33R11. The clock is derived from theSYSCLKI, ...
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NAME PIN SDATA[0] W2 SDATA[1] Y4 SDATA[2] Y2 SDATA[3] Y5 SDATA[4] Y3 SDATA[5] W5 SDATA[6] V5 SDATA[7] W6 SDATA[8] V6 SDATA[9] W4 SDATA[10] V4 SDATA[11] V2 SDATA[12] V3 SDATA[13] V1 SDATA[14] W3 SDATA[15] W1 SDATA[16] Y16 SDATA[17] Y17 SDATA[18] V18 ...
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NAME PIN TTIP R1, R2 TRING T1,T2 RTIP K1 RRING M1 T1/E1/J1 TRANSMIT FRAMER INTERFACE TSERI E3 TCLKT D2 TCHBLK A2 TCHCLK G1 TSSYNC A5 TSYNC C1 TSYSCLK E4 TYPE T1/E1/J1 ANALOG LINE INTERFACE Transmit Analog Tip Output for the ...
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NAME PIN TYPE TSIG B4 ETHERNET MAPPER TRANSMIT SERIAL INTERFACE TSERO E2 TCLKE F1 TDEN/ D5 TBSYNC T1/E1/J1 RECEIVE FRAMER INTERFACE RSERO H2 RCLKO G3 RCHBLK A1 RCHCLK G2 Transmit Signaling Input for the T1/E1/J1 Transceiver: When enabled, this input ...
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NAME PIN RSYNC G4 RSYSCLK F4 RFSYNC A3 RMSYNC U3 RSIG L3 TYPE Receive Sync for the T1/E1/J1 Transceiver: An extracted pulse, one RCLKO wide, is output at this pin, which identifies either frame (TR.IOCR1 multiframe (TR.IOCR1.5 ...
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NAME PIN TYPE ETHERNET MAPPER RECEIVE SERIAL INTERFACE RSERI H1 RCLKI F2 RDEN/ P2 RBSYNC T1/E1/J1 FRAMER/LIU INTERIM SIGNALS RDCLKI M4 RDCLKO M3 RNEGI L4 RNEGO N2 RPOSI J3 RPOSO N3 RDATA H3 TDCLKI D1 Receive Serial Data Input to ...
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NAME PIN TYPE TDCLKO C2 TNEGI C3 TNEGO D3 TPOSI B3 TPOSO E1 TDATA A4 TESO D4 Transmit Clock Output from the T1/E1/J1 Framer: Buffered O clock that is used to clock data through the transmit-side formatter (either TCLKT or ...
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NAME PIN LIUC B2 RST A8 TSTRST C4 MODEC[0], B19, MODEC[1] B20 QOVF H18 RLOS/LTC N1 RCL B5 RSIGF P3 TYPE HARDWARE AND STATUS PINS Line Interface Unit Connect: When a logic low is present on this input pin, the ...
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NAME PIN TYPE SYSCLKI V8 MCLK H4 BPCLK B1 8XCLK K4 XTALD J4 SYSTEM CLOCKS System Clock In for Ethernet Mapper: 100MHz System Clock input to the DS33R11, used for internal operation. This clock is I buffered and provided at ...
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NAME PIN TYPE JTCLK1 A7 JTDI1 C9 JTDO1 B7 JTMS1 C8 JTRST1 C7 JTCLK2 A6 JTDI2 B6 JTDO2 C5 JTMS2 B9 JTRST2 B8 JTAG INTERFACE JTAG Clock 1 for the Ethernet Mapper: This signal is used to Ipu shift data ...
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NAME PIN TYPE RVDD K3, L1 J1, J2, K2, RVSS L2, M2 TVDD U1 P1, R3, T3, TVSS U2 D1–D17, DVDD E17 N4, P4, R4, DVSS T4 B10, B15, C12, F3, J18, J20, VDD1.8 P18, P19, R19, R20, V9, Y9, ...
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Figure 7-1. 256-Ball BGA Pinout RCHBLK TCHBLK RFSYNC TDATA TSSYNC JTCLK2 B BPCLK LIUC TPOSI TSIG RCL JTDI2 C TSYNC TDCLKO TNEGI TSTRST JTDO2 N.C. TDEN/ D TDCLKI TCLKT TNEGO TESO N.C. TBSYNC ...
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FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet packet LANs and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packet arbiter, committed information rate controller (CIR), HDLC/X.86 (LAPS) mapper, ...
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Both the transmit and receive path of the integrated T1/E1/J1 transceiver also have two HDLC controllers. The HDLC controllers transmit and receive data through the framer block. The HDLC controllers can be assigned to any time slot, group of time ...
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ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can ...
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Figure 9-1. Clocking for the DS33R11 CLAD TTIP MUX TRING BERT RTIP MUX RRING JTAG2 NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED T1/E1/J1 TANSCEIVER ARE DISCUSSED IN SECTION 10.1. HDLC HDLC 44 of 344 μP Port CLAD SYSCLKI REF_CLKO ...
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Ethernet Interface Clock Modes The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation. Table 9-1 outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is generated by division of ...
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Resets and Low Power Modes The external RST pin and the global reset bit in signal resets the status and control registers on the chip (except the GL.CR1.RST bit) to their default values and resets all the other flops ...
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Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits outlined in Section ...
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Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global ...
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Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count ...
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Interrupt Information Registers The interrupt information registers provide an indication of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read TR.IIR1 and TR.IIR2 to quickly identify which of the nine ...
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Connections and Queues The multi-port devices in this product family provide bidirectional cross-connections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device to provide software compatibility ...
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It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure ...
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Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33R11 allows for optional flow control based on the queue high watermark or through host processor intervention. There ...
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Full Duplex Flow Control Automatic flow control is enabled by default. The host processor can disable this functionality with SU.GCR.ATFLOW. The flow control mechanism is governed by the high watermarks (SU.RQHT). The low threshold can be used as indication ...
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Figure 9-3. Flow Control Using Pause Control Frame Receive Queue Growth 9.13.2 Half Duplex Flow Control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of ...
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Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100Mbit/s MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains seven signals with a reference clock ...
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The MAC circuitry generates a frame status for every frame that is received. This real time status can be read by SU.RFSB0 to SU.RFSB3. Note the frame status is the “real time” status and hence the value will change as ...
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DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can ...
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Figure 9-6. DS33R11 Configured as a DCE in MII Mode 9.15 Ethernet MAC Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the SU.MACWD0-3 registers to be written with 4 bytes of data. ...
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Table 9-6. MAC Control Registers ADDRESS REGISTER 0000h-0003h SU.MACCR 0014h-0017h SU.MACMIIA 0018h-001Bh SU.MACMIID 001Ch-001Fh SU.MACFCR 0100h-0103h SU.MMCCTRL Table 9-7. MAC Status Registers ADDRESS REGISTER 0200h-0203h SU.RxFrmCtr 0204h-0207h SU.RxFrmOkCtr 0300h-0303h SU.TxFrmCtr 0308h-030Bh SU.TxBytesCtr 030Ch-030Fh SU.TxBytesOkCtr 0334h-0337h SU.TxFrmUndr 0338h-033Bh SU.TxBdFrmCtr DESCRIPTION MAC ...
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MII Mode Options The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section ...
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PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of ...
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Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the ...
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Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next ...
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Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream is ...
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Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The ...
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Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in ...
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X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides HDLC type framing structure for encapsulation of Ethernet frames. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. ...
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Figure 9-13. X.86 Encapsulation of the MAC frame Flag(0x7E) Address(0x04) Control(0x03) 1st Octect of SAPI(0xfe) 2nd Octect of SAPI(0x01) Destination Adrs(DA) Source Adrs(SA) Length/Type MAC Client Data PAD FCS for MAC FCS for LAPS Flag(0x7E) MSB The DS33R11 will encode ...
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The X86 received frame is aborted if: • If 7d,7E is detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 octets. • Control, SAPI and address field ...
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Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC data to a programmable rate. The CIR location is shown in the the Receive MAC to Transmit ...
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INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only ...
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Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 0 0 The TCLKT pin (C) is always the source of transmit clock. Switch to the recovered clock (B) when the signal at the TCLKT pin 0 1 fails to transition after ...
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T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the transceiver has ...
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T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt (TR.T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern ...
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E1 Framer/Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has ...
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Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (TR.E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are ...
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Error Counters The transceiver contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register ...
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Path Code Violation Count Register (TR.PCVCR mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF ...
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Frames Out-of-Sync Count Register (TR.FOSCR mode, TR.FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count ...
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DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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Signaling Operation There are two methods to access receive signaling data and provide transmit signaling data, processor-based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG ...
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Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
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Figure 10-3. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 10.9.3 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On multiframe boundaries, ...
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E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
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Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the device, ...
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Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh Write TR.IAAR = 02h ;select channel 3 in the array Write TR.PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
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Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can ...
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Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled, a 1.544MHz ...
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G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSERI already has the FAS/NFAS, CRC multiframe alignment word, and ...
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T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 10.14.1 Transmit BOC Bits ...
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Additional (Sa) and International (Si) Bit Operation (E1 Only) When operated in the E1 mode, the transceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.RAF/TR.RNAF and TR.TAF/TR.TNAF registers ...
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Additional HDLC Controllers in T1/E1/J1 Transceiver This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each ...
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Table 10-12. HDLC Controller Registers REGISTER TR.H1TC, HDLC #1 Transmit Control Register TR.H2TC, HDLC #2 Transmit Control Register TR.H1RC, HDLC #1 Receive Control Register TR.H2RC, HDLC #2 Receive Control Register TR.H1FC, HDLC #1 FIFO Control Register TR.H2FC, HDLC #2 FIFO ...
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FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
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FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
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Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that existed in the previous generation of the T1 framer. In new applications recommended that ...
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Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TR.TFDL). When a new ...
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Programmable In-Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To ...
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Line Interface Unit (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface ...
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Receive Level Indicator and Threshold Interrupt The device reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in Information Register 2 (TR.INFO2). This feature is helpful when trouble-shooting line-performance problems. The device can initiate ...
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Transmitter The transceiver uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the line. The waveforms created by the device meet the latest ETSI, ITU-T, ANSI, ...
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MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 ...
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Recommended Circuits Figure 10-7. Basic Interface TRANSMIT LINE RECEIVE LINE NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE 2: RESISTORS R SHOULD BE SET TO 60Ω EACH IF THE INTERNAL RECEIVE-SIDE TERMINATION FEATURE IS ENABLED. WHEN THIS FEATURE IS ...
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Figure 10-8. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 10-9. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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Figure 10-10. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 10-11. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DEVICE TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DEVICE TOLERANCE 1.5 MINIMUM ...
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Figure 10-12. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 10-13. Jitter Attenuation (E1 Mode) 0 -20 -40 - MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area E1 MODE 10 100 1k FREQUENCY (Hz) 107 ...
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Figure 10-14. Optional Crystal Connections NOTE: C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE. 10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION The BERT block ...
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Figure 10-15. Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 10-16. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO ...
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BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern Daly pattern. For a repetitive pattern that is fewer than ...
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Payload Error-Insertion Function (T1 Mode Only) An error-insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 ...
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Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKO). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common ...
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T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram HSIE1-3 through PCPR ESCR.4 TESE TLINK H1TC.4 HDLC FDL #1 THMS1 H2TC.4 HDLC FDL #2 THMS2 TFDL Tx FDL T1TCR2.5 Zero TZSE Stuffer T1TCR1.2 FDL Mux TFDLS BOC Mux ...
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From BOC Mux BERT Engine T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 NOEL != 0 ERC.4 CE PEICS1-3 T1CCR1.1 PDE CRC Calculation T1TCR2.7 B8ZSE T1TCR1.1 TBL IOCR1.0 ODF CCR1.4 ODM From ESF From F-bit Mux Yellow Alarm FDL Mux ESF Yellow CRC Mux ...
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Figure 10-18. E1 Transmit Flow Diagram HSIE1-4 through PCPR ESCR.4 TESE LBCR1.1 PLB KEY - PIN - SELECTOR - REGISTER TSER TSIG Hardware Signaling TX ESTORE Estore Mux TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload HDLC Loopback Mux Engine ...
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From Idle From Idle Code Mux Code Mux Per-Channel Per-Channel Loopback Loopback TNAF TNAF Sa-bit Mux Sa-bit Mux Si-bit Mux Si-bit Mux E1TCR1.4 TSIS E1TCR1.4 TSIS E1TCR1.0 TCRC4 E1TCR1.0 TCRC4 Si/CRC4 Mux Si/CRC4 Mux Auto E- Auto E- E1TCR2.2 AEBE ...
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DEVICE REGISTERS Ten address lines are used to address the register space. The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global Registers are preserved for software compatibility with multiport devices. ...
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Register Bit Maps Table 11-2, Table 11-3, Table 11-4, Bits that are reserved are noted with a single dash “-“. All registers not listed are reserved and should be initialized with a value of 00h for proper operation, unless ...
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Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map DDR AME IT 40h AR.RQSC1 RQSC7 41h AR.TQSC1 TQSC7 11.1.3 BERT Register Bit Map Table 11-4. BERT Register Bit Map DDR ...
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Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map DDR AME IT 0C0h LI.TSLCR - 0C1h LI.RSTPD - 0C2h LI.LPBK - 0C3h - Reserved 0C4h - LI.TPPCL 0C5h LI.TIFGC TIFG7 0C6h LI.TEPLC ...
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DDR AME IT 114h RSPC7 LI.RSPCB0 115h LI.RSPCB1 RSPC15 116h LI.RSPCB2 RSPC23 118h LI.RBC0 RBC7 119h LI.RBC1 RBC15 11Ah LI.RBC2 RBC23 11Bh RBC31 LI.RBC3 11Ch LI.RAC0 REBC7 11Dh LI.RAC1 REBC15 11Eh LI.RAC2 REBC23 11Fh LI.RAC3 REBC31 ...
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Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map DDR AME IT 140h SU.MACRADL MACRA7 141h SU.MACRADH MACRA15 142h SU.MACRD0 MACRD7 143h SU.MACRD1 MACRD15 144h MACRD23 SU.MACRD2 145h MACRD31 SU.MACRD3 146h SU.MACWD0 ...
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MAC Register Bit Map Table 11-7. MAC Indirect Register Bit Map DDR AME IT SU.MACCR 0000h Reserved 31:24 0001h 23:16 DRO 0002h 15:8 Reserved 0003h 7:0 BOLMT1 0004h Reserved Reserved 0005h Reserved Reserved 0006h Reserved ...
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DDR AME IT 112h RESERVED – Reserved initialize to FF 113h RESERVED – Reserved initialize to FF 200h SU.RxFrmCtr RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24 31:24 201h 23:16 RXFRMC23 RXFRMC22 RXFRMC21 RXFRMC20 RXFRMC19 RXFRMC18 ...
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Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = AME IT R 000 — h TR.MSTRREG 001 RSMS h TR.IOCR1 002 RDCLKIN h V TR.IOCR2 003 — h TR.T1RCR1 004 — h ...
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AME 01A LSPARE h TR.SR3 01B LSPARE h TR.IMR3 01C RAIS-CI h TR.SR4 01D RAIS-CI h TR.IMR4 01E — h TR.SR5 01F — h TR.IMR5 020 — h TR.SR6 021 — h ...
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AME 035 TFPT h TR.E1TCR1 036 Reserved h TR.E1TCR2 037 — h TR.BOCC 038 CH8 h TR.RSINFO1 039 CH16 h TR.RSINFO2 03A CH24 h TR.RSINFO3 03B — h TR.RSINFO4 03C CH8 h ...
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AME 050 h TR.TS1 051 h TR.TS2 052 h TR.TS3 053 h TR.TS4 054 h TR.TS5 055 h TR.TS6 056 h TR.TS7 057 h TR.TS8 058 h TR.TS9 059 h TR.TS10 05A ...
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AME IT R 06A h TR.RS11 06B h TR.RS12 06C h TR.RS13 06D h TR.RS14 06E h TR.RS15 06F h TR.RS16 070 — h TR.CCR1 071 — h TR.CCR2 072 — h TR.CCR3 073 RLT3 ...
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AME IT R 085 CH16 h TR.RCICE2 086 CH24 h TR.RCICE3 087 CH32 h TR.RCICE4 088 CH8 h TR.RCBR1 089 CH16 h TR.RCBR2 08A CH24 h TR.RCBR3 08B CH32 h TR.RCBR4 08C CH8 h TR.TCBR1 ...
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AME IT R 0A0 NOFS h TR.H2TC 0A1 — h TR.H2FC 0A2 RHCS8 h TR.H2RCS1 0A3 RHCS16 h TR.H2RCS2 0A4 RHCS24 h TR.H2RCS3 0A5 RHCS32 h TR.H2RCS4 0A6 RCB8SE h TR.H2RTSBS 0A7 THCS8 h TR.H2TCS1 ...
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AME IT R 0C1 TFDL7 h TR.TFDL 0C2 RFDLM7 h TR.RFDLM1 0C3 RFDLM7 h TR.RFDLM2 0C3 — h Reserved 0C5 — h Reserved 0C6 Si h TR.RAF 0C7 Si h TR.RNAF 0C8 SiF0 h TR.RSiAF ...
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AME IT R 0DC RPAT7 h TR.BRP1 0DD RPAT15 h TR.BRP2 0DE RPAT23 h TR.BRP3 0DF RPAT31 h TR.BRP4 0E0 TC h TR.BC1 0E1 EIB2 h TR.BC2 0E2 — h Reserved 0E3 BBC7 h TR.BBC1 ...
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Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: framer reset, LIU reset, device ID, and BERT interrupt status. These registers are preserved to provide code compatibility with the multiport devices in this product family. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO is turned off 1 = REF_CLKO is disabled and outputs an active low signal. 0 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default - - Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1) This bit is set the receive clock for Serial Interface ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE) Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: BERT Interrupt Status (BIS) This bit is set the BERT has an enabled interrupt generating event. Register Name: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue read pointer for connection 1. This queue pointer ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33R11 has completed the BIST Test initiated by BISTE. The pass ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bits CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency Note: Only CAS Latency of 2 ...
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Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data ...
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BERT Registers Register Name: Register Description: Register Address: Bit # 7 6 Name - PMU Default 0 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU) This bit causes a ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - QRSS Default 0 0 Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and PTF[0:4], and BSP[0:31]. When 1, the pattern ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BSP7 BSP6 Default 0 0 Bits BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Register description follows next register. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bits Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are inserted in the output data ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default - - Bit 3: Performance Monitor Update Status Latched (PMSL) This bit is set when the PMS bit transitions from Bit 2: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BEC7 BEC6 Default 0 0 Bits Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits. Register description below. Register Name: Register Description: Register Address: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BC15 BC14 Default 0 0 Bits Bit Count (BC[8:15]) Eight bits bit value. Register description below. Register Name: Register Description: Register Address: Bit ...
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Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to the Serial ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TIFG7 TIFG6 Default 0 0 Bits Transmit Inter-Frame Gapping (TIFG[7:0]) – These eight bits indicate the number of additional flags and bytes of inter-frame fill to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MEIMS TPER6 Default 0 0 Bit 7: Manual Error Insert Mode Select (MEIMS) – When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of errored packets indicated by the TPEN[7:0] bits ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TPC7 TPC6 Default 0 0 Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TBC7 TBC6 Default 0 0 Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # 7 6 Name - - Default 0 0 Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet processor block performance ...
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X.86 Registers X.86 transmit and common registers are used to control the operation of the X.86 encoder and decoder. Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: X.86 Encoding ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TRSAPIL7 TRSAPIL6 Default 0 0 Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0-7) This is the address field for the X.86 transmitter and expected value for the receiver. ...
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Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMX7 RMX6 Default 1 1 Bits Receive Maximum Packet Size (RMX[7:0]) Eight bits of a sixteen bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPL RAPL Default - - Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is set when a packet with an errored FCS is detected. Bit 6: Receive ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPIE RAPIE Default 0 0 Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RPC7 RPC6 Default 0 0 Bits Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RFPC7 RFPC6 Default 0 0 Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RAPC7 RAPC6 Default 0 0 Bits Receive Aborted Packet Count (RAPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RSPC7 RSPC6 Default 0 0 Bits Receive Size Violation Packet Count (RSPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RBC7 RBC6 Default 0 0 Bits Receive Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REBC7 REBC6 Default 0 0 Bits Receive Aborted Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # 7 6 Name - - Default 0 0 Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor block performance ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: SAPI Octet not equal to LI.RX86S.SAPIHNE will generate an interrupt. Bit 2: SAPI Octet not equal to LI.RX86S.SAPILNE will generate an interrupt. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark interrupt is enabled for TFOVFLS. Bit 2: ...
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Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACRD15 MACRD14 Default 0 0 Bits MAC Read Data 1 (MACRD8-15) One of four bytes of data read from the MAC. Valid after a read command ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACWD15 MACWD14 Default 0 0 Bits 0 – 7: MAC Write Data 1 (MACWD8-15) One of four bytes of data to be written to the MAC. Data has been ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACAW 15 MACAW 14 Default 0 0 Bits 0 – 7: MAC Write Address (MACAW8-15) High byte of the MAC indirect write address. Used only for write operations. Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Queue Loopback Enable (QLP) If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: No Carrier Queue Flush Bar (NCFQ) If this bit is set to 1, the queue for data passing from Serial Interface to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name UR EC Default 0 0 Bit 7: Under Run (UR) When this bit is set to 1, the frame was aborted due to a data under run condition of ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FL7 FL6 Default 0 0 Bits Frame Length (FL[0:7]) These 8 bits are the low byte of the length (in bytes) of the received frame, with ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MF - Default 0 0 Bit 7: Missed Frame (MF) This bit is set the packet is not successfully received from the MAC by the packet ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMPS7 RMPS6 Default 1 1 Bits 7- 0: Receiver Maximum Frame (RMPS[0:7]) Eight bits of sixteen bit value. Register description below. Register Name: Register Description: Register Address: Bit # ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE) If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - UCFR Default 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR) When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal ...
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MAC Registers The control Registers related to the control of the individual Mac’s are shown in the following Table. The DS33R11 keeps statistics for the packet traffic sent and received. The register address map is shown in the following ...
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Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY) When set to ...
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Register Name: Register Description: Register Address: 0014h: Bit # 31 30 Name Reserved Reserved Default 0 0 0015h: Bit # 23 22 Name Reserved Reserved Default 0 0 0016h: Bit # 15 14 Name PHYA4 PHYA3 Default 0 1 0017h: ...
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Register Name: Register Description: Register Address: 0018h: Bit # 31 30 Name Reserved Reserved Default 0 0 0019h: Bit # 23 22 Name Reserved Reserved Default 0 0 001Ah: Bit # 15 14 Name MIID15 MIID14 Default 0 0 001Bh: ...
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Register Name: Register Description: Register Address: 001Ch: Bit # 31 30 Name PT15 PT14 Default 0 0 001Dh: Bit # 23 22 Name PT07 PT06 Default 0 1 001Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 001Fh: ...
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Register Name: Register Description: Register Address: 0100h: Bit # 31 30 Name Reserved Reserved Default 0 0 0101h: Bit # 23 22 Name Reserved Reserved Default 0 0 0102h: Bit # 15 14 Name Reserved Reserved Default 0 0 0103h: ...
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Register Name: Register Description: Register Address: 010Ch: Bit # 31 30 Name Reserved Reserved Default 0 0 010Dh: Bit # 23 22 Name Reserved Reserved Default 0 0 010Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 010Fh: ...
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Register Name: Register Description: Register Address: 0110h: Bit # 31 30 Name Reserved Reserved Default 0 0 0111h: Bit # 23 22 Name Reserved Reserved Default 0 0 0112h: Bit # 15 14 Name Reserved Reserved Default 0 0 0113h: ...
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Register Name: Register Description: Register Address: 0200h: Bit # 31 30 Name RXFRMC31 RXFRMC30 Default 0 0 0201h: Bit # 23 22 Name RXFRMC23 RXFRMC22 Default 0 0 0202h: Bit # 15 14 Name RXFRMC15 RXFRMC14 Default 0 0 0203h: ...
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Register Name: Register Description: Register Address: 0204h: Bit # 31 30 Name RXFRMOK31 RXFRMOK30 Default 0 0 0205h: Bit # 23 22 Name RXFRMOK23 RXFRMOK22 Default 0 0 0206h: Bit # 15 14 Name RXFRMOK15 RXFRMOK14 Default 0 0 0207h: ...
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Register Name: Register Description: Register Address: 0300h: Bit # 31 30 Name TXFRMC31 TXFRMC30 Default 0 0 0301h: Bit # 23 22 Name TXFRMC23 TXFRMC22 Default 0 0 0302h: Bit # 15 14 Name TXFRMC15 TXFRMC14 Default 0 0 0303h: ...
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Register Name: Register Description: Register Address: 0308h: Bit # 31 30 Name TXBYTEC31 TXBYTEC30 Default 0 0 0309h: Bit # 23 22 Name TXBYTEC23 TXBYTEC22 Default 0 0 030Ah: Bit # 15 14 Name TXBYTEC15 TXBYTEC14 Default 0 0 030Bh: ...
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Register Name: Register Description: Register Address: 030Ch: Bit # 31 30 Name TXBYTEOK31 TXBYTEOK30 Default 0 0 030Dh: Bit # 23 22 Name TXBYTEOK23 TXBYTEOK22 Default 0 0 030Eh: Bit # 15 14 Name TXBYTEOK15 TXBYTEOK14 Default 0 0 030Fh: ...
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Register Name: Register Description: Register Address: 0334h: Bit # 31 30 Name TXFRMU31 TXFRMU30 Default 0 0 0335h: Bit # 23 22 Name TXFRMU23 TXFRMU22 Default 0 0 0336h: Bit # 15 14 Name TXFRMU15 TXFRMU14 Default 0 0 0337h: ...
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Register Name: Register Description: Register Address: 0338h: Bit # 31 30 Name TXFRMBD31 TXFRMBD30 Default 0 0 0339h: Bit # 23 22 Name TXFRMBD23 TXFRMBD22 Default 0 0 033Ah: Bit # 15 14 Name TXFRMBD15 TXFRMBD14 Default 0 0 033Bh: ...