DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 344
DS33R11+
Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11+
Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
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16 DOCUMENT REVISION HISTORY
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
REVISION
072105
030807
New product release.
(Page 28) Corrected pin description of REF_CLK.
(Page 28) Clarified text regarding use of REF_CLKO in DCE and RMII modes.
(Page 29) Corrected pin description of MDC.
(Page 43) In Section 9.1, removed from third bullet the sentence “The user can utilize the built-
in REF_CLKO output clock to drive this input.” Also removed from the fifth bullet the sentence
“This output clock can be used as an input to REF_CLK, allowing the user to have one less
oscillator for the system.”
(Page 45) In Section 9.1.1, updated the section to show that in DCE and RMII operating modes,
the REF_CLKO signal should not be used to provide an input to REF_CLK, due to the reset
requirements in these operating modes.
(Page 46) In Section 9.2, corrected low-power mode information.
(Page 56) In Section 9.14, removed the following sentence from the first paragraph: “The
REF_CLKO output can be used to source the REF_CLK input.”
(Page 68) In Section 9.19, clarified X.86 mode synchronization.
(Page 123) In Table 11-7, corrected SU.MACCR register map.
(Page 173) Corrected SU.GCR.H10S bit definition.
(Page 183) Corrected default value for RMPS (bit 0) in the SU.RMFSRL register definition.
(Page 183) Corrected the SU.RQLT and SU.RQHT default values to zero.
(Page 186) Corrected SU.MACCR.PM and SU.MACCR.PAM bit definitions.
(Page 319) In Table 13-10, added TCLKE to TBSYNC Setup Time Minimum of 3.5ns.
(Page 334) Added a note regarding the special considerations required for dual JTAG
controllers.
© 2007 Maxim Integrated Products
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
344 of 344
DESCRIPTION
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