DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 14

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

2.12 T1/E1/J1 Framer
2.13 TDM Bus
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Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats include D4 (SLC-96) and ESF
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters for:
Timed or manual update modes
DS1 idle code generation on a per-channel basis in both transmit and receive paths
ANSI T1.403-1998 Support
RAI-CI detection and generation
AIS-CI detection and generation
E1 ETS 300 011 RAI generation
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state
Flexible signaling support
Addition of hardware pins to indicate carrier loss and signaling freeze
Automatic RAI generation to ETS 300 011 specifications
Access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Dual two-frame independent receive and transmit elastic stores
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Hardware signaling capability
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
Access to the data streams in between the framer/formatter and the elastic stores
User-selectable synthesized clock output
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T1: BPV, CV, CRC6, and framing bit errors
E1: BPV, CV, CRC4, E-bit, and frame alignment errors
User-defined
Digital milliwatt
Three independent generators and detectors
Patterns from 1 to 8 bits or 16 bits in length
Software or hardware based
Interrupt generated on change of signaling data
Receive signaling freeze on loss-of-sync, carrier loss, or frame slip
Ability to calculate and check CRC6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
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