DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 260

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Global Receive-Idle Code (GRIC). Setting this bit causes all receive channels to be set to the idle code
written to the TR.PCICR register. This bit must be set = 0 for read operations. The value in bits IAA0–IAA5 must be
a valid transmit channel (01h to 20h for E1 mode; 01h to 18h for T1 mode).
Bit 6: Global Transmit-Idle Code (GTIC). Setting this bit causes all transmit channels to be set to the idle code
written to the PCICR register. This bit must be set = 0 for read operations. The value in bits IAA0–IAA5 must be a
valid transmit channel (01h to 20h for E1 mode; 01h to 18h for T1 mode).
Bits 0 – 5: Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed with
the idle code defined in the TR.PCICR register. IAA0 is the LSB of the 5-bit channel code. Channel 1 is 01h.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Per-Channel Idle-Code Bits (C0 to C7). This register defines the idle code to be programmed in the
channel selected by the TR.IAAR register. C0 is the LSB of the idle code (this bit is transmitted last).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Transmit Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8)
GRIC
0
0
1
1
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle-code array into the transmit data stream
GTIC
GRIC
0
1
0
1
CH8
C7
7
0
7
0
7
0
Updates a single transmit or receive channel
Updates all transmit channels
Updates all receive channels
Updates all transmit and receive channels
TR.IAAR
Idle Array Address Register
7Eh
TR.PCICR
Per-Channel Idle Code Register
7Fh
TR.TCICE1
Transmit-Channel Idle-Code Enable Register 1
80h
GTIC
CH7
C6
6
0
6
0
6
0
FUNCTION
IAA5
CH6
C5
5
0
5
0
5
0
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IAA4
CH5
C4
0
0
0
4
4
4
IAA3
CH4
C3
3
0
3
0
3
0
IAA2
CH3
C2
2
0
2
0
2
0
IAA1
CH2
C1
1
0
1
0
1
0
IAA0
CH1
C0
0
0
0
0
0
0