DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 38

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

JTCLK1
JTCLK2
JTRST1
JTRST2
JTDO1
JTMS1
JTDO2
JTMS2
NAME
JTDI1
JTDI2
PIN
A7
C9
B7
C8
C7
A6
B6
C5
B9
B8
TYPE
Ipu
Ipu
Ipu
Ipu
Ipu
Ipu
Ipu
Ipu
Oz
Oz
JTAG Clock 1 for the Ethernet Mapper: This signal is used to
shift data into JTDI1 on the rising edge and out of JTDO1 on the
falling edge.
JTAG Data In 1 for the Ethernet Mapper: Test instructions and
data are clocked into this pin on the rising edge of JTCLK1. This
pin has a 10kΩ pullup resistor.
JTAG Data Out 1 for the Ethernet Mapper: Test instructions and
data are clocked out of this pin on the falling edge of JTCLK1. If not
used, this pin should be left unconnected.
JTAG Mode Select 1 for the Ethernet Mapper: This pin is
sampled on the rising edge of JTCLK1 and is used to place the test
access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTAG Reset 1 for the Ethernet Mapper: JTRST1 is used to
asynchronously reset the test access port controller. After power
up, a rising edge on JTRST1 will reset the test port and cause the
device I/O to enter the JTAG DEVICE ID mode. Pulling JTRST1
low restores normal device operation. JTRST1 is pulled HIGH
internally via a 10kΩ resistor operation. If boundary scan is not
used, this pin should be held low.
JTAG Clock 2 for the T1/E1/J1 Transceiver: This signal is used
to shift data into JTDI1 on the rising edge and out of JTDO1 on the
falling edge.
JTAG Data In 2 for the T1/E1/J1 Transceiver: Test instructions
and data are clocked into this pin on the rising edge of JTCLK2.
This pin has a 10kΩ pullup resistor.
JTAG Data Out 2 for the T1/E1/J1 Transceiver: Test instructions
and data are clocked out of this pin on the falling edge of JTCLK2.
If not used, this pin should be left unconnected.
JTAG Mode Select 2 for the T1/E1/J1 Transceiver: This pin is
sampled on the rising edge of JTCLK2 and is used to place the
test-access port into the various defined IEEE 1149.1 states. This
pin has a 10kΩ pullup resistor.
JTAG Reset 2 for the T1/E1/J1 Transceiver: JTRST2 is used to
asynchronously reset the test access port controller. After power-
up, JTRST2 must be toggled from low to high. This action will set
the device into the JTAG DEVICE ID mode. Normal device
operation is restored by pulling JTRST2 low. JTRST2 is pulled HIGH
internally via a 10kΩ resistor operation.
JTAG INTERFACE
38 of 344
FUNCTION