DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 327

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
13.9 AC Characteristics: Receive-Side
Table 13-14. AC Characteristics: Receive Side
(V
RDCLKO Period
RDCLKO Pulse Width
RDCLKO Pulse Width
RDCLKI Period
RDCLKI Pulse Width
RSYSCLK Period
RSYSCLK Pulse Width
RSYNC Setup to RSYSCLK Falling
RSYNC Pulse Width
RPOSI/RNEGI Setup to RDCLKI Falling
RPOSI/RNEGI Hold from RDCLKI Falling
RSYSCLK, RDCLKI Rise and Fall Times
Delay RDCLKO to RPOSO, RNEGO
Valid
Delay RCLKO to RSERO, RDATA, RSIG
Valid
Delay RCLKO to RCHCLK, RSYNC,
RCHBLK, RFSYNC
Delay RSYSCLK to RSERO, RSIG Valid
Delay RSYSCLK to RCHCLK, RCHBLK,
RMSYNC, RSYNC
Note 1: Timing parameters in this table are guaranteed by design (GBD).
Note 2: Jitter attenuator enabled in the receive path.
Note 3: Jitter attenuator disabled or enabled in the transmit path.
Note 4: RSYSCLK = 1.544MHz.
Note 5: RSYSCLK = 2.048MHz.
DD
= 3.3V ± 5%, T
PARAMETER
A
= -40°C to +85°C.) (Note 1,
SYMBOL
t
t
R
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Figure
t
t
t
t
PW
CH
HD
DD
LP
LH
LH
CP
CL
SP
SH
SL
SU
SU
D1
D2
D3
D4
LL
LL
, t
F
327 of 344
13-3,
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 4)
(Note 5)
CONDITIONS
Figure
13-14, and
MIN
200
200
150
150
20
20
20
20
20
50
20
20
Figure
488 (E1)
488 (E1)
648 (T1)
648 (T1)
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
13-15)
TYP
648
488
CP
CP
LP
LP
LP
LP
SP
SP
MAX
22
50
50
50
22
22
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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