DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 234

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: RSERO Control (RSERC)
Bit 6: Receive Signaling Mode Select (RSIGM)
Bit 5: Receive HDB3 Enable (RHDB3)
Bit 4: Receive G.802 Enable (RG802). See Section
Bit 3: Receive CRC4 Enable (RCRC4)
Bit 2: Frame Resync Criteria (FRC)
Bit 1: Sync Enable (SYNCE)
Bit 0: Resync (RESYNC). When toggled from low to high, a resync is initiated. Must be cleared and set again for a
subsequent resync.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Receive Carrier-Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a receive carrier-loss
condition for both the framer and LIU.
0 = allow RSERO to output data as received under all conditions
1 = force RSERO to 1 under loss-of-frame alignment conditions
0 = CAS signaling mode
1 = CCS signaling mode
0 = HDB3 disabled
1 = HDB3 enabled
0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
0 = CRC4 disabled
1 = CRC4 enabled
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
0 = auto resync enabled
1 = auto resync disabled
0 = RCL declared upon 255 consecutive 0s (125μs)
1 = RCL declared upon 2048 consecutive 0s (1ms)
RSERC
7
0
7
0
TR.E1RCR1
E1 Receive Control Register 1
33h
TR.E1RCR2
E1 Receive Control Register 2
34h
RSIGM
6
0
6
0
RHDB3
5
0
5
0
234 of 344
RG802
10.10
0
0
4
4
for details.
RCRC4
3
0
3
0
FRC
2
0
2
0
SYNCE
1
0
1
0
RESYNC
RCLA
0
0
0
0

Related parts for DS33R11+