DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 252

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 1 – 2: Backplane Clock Selects (BPCS0, BPCS1)
Bit 0: Backplane Clock Enable (BPEN)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Multiframe Sync Source (TMSS). Should be set = 0 only when transmit hardware signaling is
enabled.
Bit 6: Interrupt Disable (INTDIS). This bit is convenient for disabling interrupts without altering the various
interrupt mask register settings.
Bit 3: Transmit Channel-Data Format (TDATFMT)
Bit 2: Transmit Gapped-Clock Enable (TGPCKEN)
Bit 1: Receive Channel-Data Format (RDATFMT)
Bit 0: Receive Gapped-Clock Enable (RGPCKEN)
BPCS1
0
0
1
1
0 = disable BPCLK pin (pin held at logic 0)
1 = enable BPCLK pin
0 = elastic store is source of multiframe sync
1 = framer or TSYNC pin is source of multiframe sync
0 = interrupts are enabled according to the various mask register settings
1 = interrupts are disabled regardless of the mask register settings
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = TCHCLK functions normally
1 = enable gapped bit-clock output on TCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = RCHCLK functions normally
1 = enable gapped bit-clock output on RCHCLK
TMSS
7
0
BPCS0
—
7
0
0
1
0
1
INTDIS
6
0
TR.CCR2
Common Control Register 2
71h
TR.CCR3
Common Control Register 3
72h
—
BPCLK Frequency (MHz)
6
0
—
5
0
16.384
8.192
4.096
2.048
—
5
0
—
4
0
252 of 344
TDATFMT
—
0
4
3
0
—
3
0
TGPCKEN
2
0
BPCS1
2
0
RDATFMT
1
0
BPCS0
1
0
RGPCKEN
0
0
BPEN
0
0