TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 188

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

(Note 1)
(Note 2)
Data write timing to transmit
buffer or shift register
•
If the CTS signal is set to “H” during transmission, the next data transmission is
suspended after the current transmission is completed.
Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to
“L.”
Handshake function
TXDCLK
The CTS pin enables frame by frame data transmission so that overrun errors can be
prevented. This function can be enabled or disabled by SC0MOD0 <CTSE>.
When the
but the next data transmission is suspended until the
However in this case, the INTTX0 interrupt is generated, the next transmit data is requested
to the CPU, data is written to the transmit buffer, and it waits until it is ready to transmit data.
Although no RTS pin is provided, a handshake control function can be easily implemented
by assigning a port for the RTS function. By setting the port to “H” level upon completion of
data reception (in the receive interrupt routine), the transmit side can be requested to
suspend data transmission.
SIOCLK
CTS
TXD
①
Fig. 10-7 CTS (Clear to Transmit) Signal Timing
CTS pin is set to the “H” level, the current data transmission can be completed
Transmit side
Transmission is
suspended during
this period
0
Fig. 10-6 Handshake Function
CTS
TXD
13
14
②
TMPM370 10-17
15
16
1
start bit
2
RXD
3
RTS (Any port)
Receive side
CTS pin returns to the “L” level.
14
0
15
16
Serial Channel
1
bit 0
TMPM370
2
3