TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 56

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

（１）Disabling interrupt by CPU
（２）CPU interrupt registers setting
7.5.2.2
any unexpected interrupt on the way.
basically. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then
enable the interrupt by the CPU.
unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt
in the clock generator and then enable the interrupt.
them.
When preparing for an interrupt, it is needed to pay attention to the order of configuration to avoid
Initiating an interrupt or changing its configuration must be implemented in the following order
To configure the clock generator, you must follow the order indicated here not to cause any
The following sections are listed in the order of interrupt handling and describe how to configure
PRIMASK Register. All interrupts and exceptions other than non-maskable interrupts and hard
faults can be masked.
NVIC registers.
the number of bits actually used varies with each product.Priority level 0 is the highest priority
level.If multiple sources have the same priority, the smallest-numbered interrupt source has the
highest priority.
Use "MSR" instruction to set this register.
You can assign a priority level by writing to <PRI_n> field in an Interrupt Priority Register of the
Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but
(1) Disabling interrupt by CPU
(2) CPU registers setting
(3) Preconfiguration 1 (Interrupt from external pin）
(4) Preconfiguration 2 (interrupt from peripheral function）
(5) Preconfiguration 3 (interrupt Set-Pending Register）
(6) Configuring the clock generator
(7) Enabling interrupt by CPU
To make the CPU for not accepting any interrupt, write “1” to the corresponding bit of the
Preparation
●Interrupt mask register
PRIMASK
(Note1)
(Note2)
PRIMASK register cannot be modified by the user access level.
If a fault causes when “1” is set to the PRIMASK register, it is
treated as a hard fault.
TMPM370 7-18
←
“1”(interrupt disabled)
TMPM370
Interrupt