TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 59

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

（１）Pushing during ISR
（２）Clearing interrupt factor
7.5.2.3
7.5.2.4
7.5.2.5
7.5.2.6
according to the active level specified in the clock generator, and is notified to the CPU.
level-sensitive interrupt request must be held at the active level until it is detected, otherwise the
interrupt request will cease to exist when the signal level changes from active to inactive.
"High" level to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear
(CGICRCG) Register. If a standby mode is exited without clearing the interrupt request, the same
interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt
request in the ISR.
stack then enter the ISR.
describes what is recommended at the service routine programming and how the factor is cleared.
Cortex-M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No
extra programming is required for them.
being executed. We recommend you to push the contents of general-purpose registers that might
be rewritten.
cleared with the CG Interrupt Request Clear (CGICRCG) register.
If an interrupt source is used for exiting a standby mode, an interrupt request is detected
When the clock generator detects an interrupt request, it keeps sending the interrupt signal in
The CPU detects an interrupt with the highest priority.
On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the
An ISR requires specific programming according to the application to be used. This section
An ISR normally pushes register contents to the stack and handles an interrupt as required. The
Push the contents of other registers if needed.
Interrupt with the higher priority and exceptions such as NMI are accepted even when an ISR is
If an interrupt source is used for clearing a standby mode, each interrupt request must be
An edge-triggered interrupt request, once detected, is held in the clock generator. A
Detection by Clock Generator
Detection by CPU
CPU processing
Interrupt Service Routine (ISR)
TMPM370 7-21
TMPM370
Interrupt