TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 193

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

10.3.16 Direction of Data Transfer
10.3.17 Stop Bit Length
10.3.18 Status Flag
In the I/O interface mode, the direction of data transfer can be switched between “MSB first”
and “LSB first” by the data transfer direction setting bit <DRCHG> of the SC0MOD2 serial
mode control register 2. Don't switch the direction when data is being transferred.
In the UART transmission mode, the stop bit length can be set to either 1 or 2 bits by bit 4
<SBLEN> of the SC0MOD2 register. In the receive side, the stop bit is always regarded as
1 bit.
If the double buffer function is enabled (SC0MOD2 <WBUF> = “1”), the bit 6 flag <RBFLL>
of the SC0MOD2 register indicates the condition of receive buffer full. When one frame of
data has been received and transferred from buffer 1 to buffer 2, this bit is set to “1” to show
that buffer 2 is full (data is stored in buffer 2). When the receive buffer is read by CPU, it is
cleared to “0.” If <WBUF> is set to “0,” this bit is insignificant and must not be used as a
status flag. When double buffering is enabled (SC0MOD2 <WBUF> = “1”), the bit 7 flag
<TBEMP> of the SC0MOD2 register indicates that Transmit Buffer 2 is empty. When data is
moved from Transmit Buffer 2 to Transmit Buffer 1 (shift register), this bit is set to “1”
indicating that Transmit Buffer 2 is now empty. When data is set to the transmit buffer by
Note)
3. Framing error <FERR>: Bit 2 of the SC0CR register
and the operation is undefined. If Transmit Buffer 2 is disabled, the under-run flag
<PERR> will not be set. This flag is set to “0” when it is read.
In the UART mode, this bit is set to “1” when a framing error is generated. This flag is
set to “0” when it is read. A framing error is generated if the corresponding stop bit is
determined to be “0” by sampling the bit at around the center. Regardless of the
<SBLEN> (stop bit length) setting of the serial mode control register 2, SC0MOD2, the
stop bit status is determined by only 1 bit on the receive side.
Operation mode
UART
I/O Interface
(SCLK input)
I/O Interface
(SCLK output)
Changing the mode from I/O interface SCLK output mode to the other
mode, read SC0CR to clear SC0CR<PERR> flag.
TMPM370 10-22
Error flag
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
Function
Fixed to 0 (WBUF = 0)
Fixed to 0
Operation undefined
Operation undefined
Fixed to 0
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag (WBUF = 1)
Serial Channel
TMPM370