TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 301

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

Bits 5, 3, 1
Bits 5, 3, 1
Upper
phase
Upper
phase
16.3.3.2 PMD Output Control Register (PMDnMDOUT)
Output Control
Output Control
<UOC, VOC, WOC>,<UPWM, VPWM,WPWM>: U-, V-, and W-phase output control
○PMDnMDCR<SYNTMD>=0
Polarity: Active high (MDPOT bits 3, 2=1)
0
0
1
1
○PMDnMDCR<SYNTMD>=1
Polarity: Active high (MDPOT bits 3, 2=1)
0
0
1
1
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
Table 16-3 Port Outputs according to the UOC, VOC, WOC, UPWM, VPWM and WPWM Settings
MDOUT
MDOUT
The MDOUT register controls the port outputs of the U, V and W phases (see Table 16-3 below.)
* To load the second buffer of MDOUT with a value updated via the bus, select the bus mode (default)
* Do not write to this register in byte units. If the upper 8 bits [15:8] and the lower 8 bits [7:0] are written
by setting MODESEL<MDSEL> to 0.
separately, operation cannot be guaranteed.
Bits 4, 2, 0
Bits 4, 2, 0
Lower
phase
Lower
phase
0
1
0
1
0
1
0
1
R → 0
R → 0
R → 0
R → 0
(PMD0:0x4005 0428, PMD1:0x4005 04A8)
31
23
15
0
0
0
7
0
-
-
-
-
output
output
Upper
phase
Upper
phase
0: H/L output
0: H/L output
H
H
H
H
L
L
L
L
H/L or PWM Output Select
H/L or PWM Output Select
MDOUT Bits 10, 9, 8
MDOUT Bits 10, 9, 8
R → 0
R → 0
R → 0
R → 0
output
output
Lower
phase
Lower
phase
30
22
14
0
0
0
6
0
-
-
-
-
H
H
H
H
L
L
L
L
Upper
phase
output
/PWM
Upper
phase
output
/PWM
PWM
PWM
PWM
PWM
1: PWM output
1: PWM output
L
L
R → 0
R → 0
R → 0
29
21
13
0
0
0
5
0
-
-
-
TMPM370 16-17
Lower
phase
output
/PWM
Lower
phase
output
/PWM
/PWM
PWM
PWM
PWM
WOC
R/W
L
L
R → 0
R → 0
R → 0
Polarity: Active low (MDPOT bits 3, 2=0)
Polarity: Active low (MDPOT bits 3, 2=0)
28
20
12
0
0
0
4
0
-
-
-
Bits 5,3,1
Bits 5,3,1
Upper
phase
Upper
phase
Output Control
Output Control
0
0
1
1
0
0
1
1
MDOUT
MDOUT
R → 0
R → 0
R → 0
27
19
11
0
0
0
3
0
-
-
-
Bits 4,2,0
Bits 4,2,0
Lower
phase
Lower
phase
VOC
R/W
0
1
0
1
0
1
0
1
WPWM
R → 0
R → 0
R/W
26
18
10
0
0
0
2
0
-
-
Upper
phase
output
Upper
phase
output
0: H/L output
0: H/L output
H
H
H
H
L
L
L
L
H/L or PWM Output Select
H/L or PWM Output Select
MDOUT Bits 10, 9, 8
MDOUT Bits 10, 9, 8
Motor control circuit
VPWM
Lower
phase
output
Lower
phase
output
R → 0
R → 0
R/W
25
17
H
H
H
H
0
0
9
0
1
0
L
L
L
L
-
-
UOC
R/W
Upper
phase
output
/PWM
/PWM
Upper
phase
output
/PWM
/PWM
PWM
PWM
1: PWM output
1: PWM output
H
H
UPWM
R → 0
R → 0
TMPM370
R/W
24
16
0
0
8
0
0
0
-
-
phase
output
/PWM
/PWM
phase
output
/PWM
Lower
Lower
PWM
PWM
PWM
H
H