TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 91

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

This resister set the clearing standby request active level of external interrupt INT4 to INT7.
CGIMCGB
7.6.3.2
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
(Note1)
(Note2)
CG Interrupt Mode Control Register B
EMSTxx is effective only when EMCGxx is set to "100" for both rising and falling
edge. The active level used for the reset of standby can be checked by referring
EMSTxx. If interrupts are cleared with the CGICRCG register, EMSTxx is also
cleared.
Please specify the bit for the edge first and then specify the bit for the <INTxEN>.
Setting them simultaneously is prohibited.
“0” is read Active state setting of INT4 standby
“0” is read Active state setting of INT5 standby
“0” is read Active state setting of INT6 standby
“0” is read Active state setting of INT7 standby
15
23
31
7
R
R
R
R
0
0
0
0
clear request. (101 to 111: setting
prohibited)
clear request. (101 to 111: setting
prohibited)
clear request. (101 to 111: setting
prohibited)
clear request. (101 to 111: setting
prohibited)
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
EMCG42
EMCG52
EMCG62
EMCG72
14
22
30
6
0
0
0
0
TMPM370 7-53
EMCG41
EMCG51
EMCG61
EMCG71
R/W
R/W
R/W
R/W
13
21
29
5
1
1
1
1
EMCG40
EMCG50
EMCG60
EMCG70
12
20
28
4
0
0
0
0
standby clear request
standby clear request
standby clear request
standby clear request
Active state of INT4
Active state of INT5
Active state of INT6
Active state of INT7
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
EMST41
EMST51
EMST61
EMST71
19
27
11
3
0
0
0
0
R
R
R
R
EMST40
EMST50
EMST60
EMST70
10
18
26
2
0
0
0
0
Reads as
undefined.
Reads as
undefined.
Reads as
undefined.
Reads as
undefined.
Undefined
Undefined
Undefined
Undefined
17
25
1
R
9
R
R
R
INT4 clear
input
0: Disable
1: Enable
INT5 clear
input
0: Disable
1: Enable
INT6 clear
input
0: Disable
1: Enable
INT7 clear
input
0: Disable
1: Enable
INT5EN
INT7EN
TMPM370
INT4EN
INT6EN
Interrupt
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0