TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 428

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

(Note) If the serial operation mode is determined as UART, the boot program checks if the SIO can
(Note) The upper four bits of the ACK response are the same as those of the previous command
(Note) The upper four bits of the ACK response are the same as those of the operation command
5)
Acknowledge Responses
The boot program represents processing states with specific codes. Table 20-10 to Table 20-13 show
the values of possible acknowledge responses to the received data. The upper four bits of the
acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates
a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1
and bit 2 are always 0. Receive error checking is not done in I/O Interface mode.
be programmed to the baud rate at which the operation mode byte was transferred. If that
baud rate is not possible, the boot program aborts, without sending back any response.
code.
code. It is 1 ( N＝RAM transfer command data [7:4] ) when password error occurs.
0xN8 (See Note)
0xN1 (See Note)
0xN8 (See Note)
0xN1 (See Note)
0xN0 (See Note)
Return Value
Return Value
Return Value
Return Value
0x54
0x4F
0x4C
0x86
0x30
0x10
0x20
0x30
0x40
Table 20-13 ACK Response to Chip and Protection Bit Erase Byte
Table 20-10 ACK Response to the Serial Operation Mode Byte
Table 20-12 ACK Response to the Checksum Byte
Table 20-11 ACK Response to the Command Byte
The Chip Erase enabling command was received.
The Chip Erase command was completed.
The Chip Erase command was abnormally completed.
The SIO can be configured to operate in UART mode. (See Note)
The SIO can be configured to operate in I/O Interface mode.
A receive error occurred while getting a command code.
An undefined command code was received. (Reception was completed normally.)
The RAM Transfer command was received.
The Show Flash Memory Sum command was received.
The Show Product Information command was received.
The Chip Erase command was received.
A receive error occurred.
A checksum or password error occurred.
The checksum was correct.
TMPM370 20-36
Meaning
Meaning
Meaning
Meaning
Flash Memory Operation
TMPM370