TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 228

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

11.4 Operation
(Note 1) The counter of the watchdog timer stops at the debug mode.
The watchdog timer generates the NMI or an internal reset after a lapse of the detection time specified
by the WDMOD <WDTP2: 0> register. Before generating the NMI or an internal reset, the binary
counter for the watchdog timer must be cleared to "0" using software (instruction). If the CPU
malfunctions (runaways) due to noise or other disturbances and cannot execute the instruction to
clear the binary counter, the binary counter overflows and the non-maskable interrupt by the NMI or
an internal reset is generated. The CPU is able to recognize the occurrence of a malfunction
(runaway) by identifying the non-maskable interrupt and to restore the faulty condition to normal by
using a malfunction (runaway) countermeasure program.
The watchdog timer begins operation immediately after a reset is cleared.
on the WDMOD <I2WDT> setting. Before putting it in IDLE mode, WDMOD <I2WDT> must be set to
an appropriate setting, as required.
In STOP mode, the watchdog timer is reset and in an idle state. In IDLE mode, its operation depends
Example:
1. To clear the binary counter
2. To set the detection time of the watchdog timer to 2
3. To disable the watchdog timer.
WDMOD ← 1 0 0 1
WDMOD ← 0
WDCR
WDCR
← 0 1 0 0 1 1 1 0
← 1 0 1 1 0 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
− − − − − − −
TMPM370 11-5
− − − −
Writes the clear code
Clears WDTE to "0"
Writes the disable code (0xB1)
17
/f
SYS.
(0x4E)
Watchdog Timer
TMPM370