Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 165

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Baud Rate
IR_RXD
UART’s
Clock
RXD
Caution:
Receiving IrDA Data
8-clock
delay
Start Bit = 0
Data received from the infrared transceiver via the IR_RXD signal through the RXD pin
is decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 24 displays data reception.
When the infrared endec is enabled, the UART’s RXD signal is internal to the Z16FMC
products when the IR_RXD signal is received through the RXD pin.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data.
When the count reaches 12 baud clock periods, the sampling window for the next incom-
ing pulse opens. The window remains open until the count again reaches 8 (i.e., 24 baud
clock periods since the previous pulse was detected). This gives the Endec a sampling
window of minus 4 baudrate clocks to plus 8 baudrate clocks around the expected time of
an incoming pulse. If an incoming pulse is detected inside this window, this process is
16-clock
min. 1.6  s
The system clock frequency must be at least 1.0 MHz to ensure proper reception
of the 1.6
period
pulse
Start Bit = 0
16-clock
period

s minimum width pulses allowed by the IrDA standard.
Data Bit 0 = 1
Figure 24. Infrared Data Reception
Data Bit 0 = 1
P R E L I M I N A R Y
16-clock
period
Data Bit 1 = 0
Data Bit 1 = 0
16-clock
period
Z16FMC Series Motor Control MCUs
Data Bit 2 = 1
Data Bit 2 = 1
16-clock
period
Infrared Encoder/Decoder
Product Specification
Data Bit 3 = 1
Data Bit 3 =
143