Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 219

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 101. I
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Note: R/W1 – bit is set (write 1) but not cleared.
Bits
7
6
5
4
3
I
2
C Control Register
Description
IEN – I
This bit enables the I
START – Send start condition
When set, this bit causes the I
condition. After assertion, this bit is cleared by the I
tion or by deasserting the IEN bit. If this bit is 1, it cannot be cleared by writing to the bit. After
this bit is set, the START condition is sent if there is data in the I2CDATA or I2CSHIFT register.
If there is no data in one of these registers, the I
bit is set while the I
the byte shifts and the acknowledge phase completes. If the STOP bit is also set, it also waits
until the STOP condition is sent before the START condition.
If START is set while a slave mode transaction is underway to this device, the START bit is
cleared and ARBLST bit in the Interrupt Status Register will be set.
STOP – Send stop condition
When set, this bit causes the I
condition after the byte in the I
been received in a receive operation. When set, this bit is reset by the I
STOP condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared
to 0 by writing to the register.
If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.
BIRQ – Baud rate generator interrupt request
This bit is ignored when the I
ler is disabled (IEN = 0) the baud rate generator is used as an additional timer causing an
interrupt to occur every time the baud rate generator counts down to one. The baud rate gener-
ator runs continuously in this mode, generating periodic interrupts.
TXI – Enable TDRE interrupts
This bit enables interrupts when the I
2
C Control Register (I2CCTL)
R/W
IEN
7
0
The I
2
C enable
2
C Control Register (see Table 101) enables and configures the I
START
R/W1
6
0
2
C Controller is shifting out data, it generates a RESTART condition after
2
C Controller.
STOP
R/W1
5
0
2
2
C Controller is enabled. If this bit is set = 1 when the I
2
2
C Controller (when configured as the Master) to send the STOP
C Shift Register has completed transmission or after a byte has
C Controller (when configured as the Master) to send the Start
P R E L I M I N A R Y
2
C Data Register is empty.
BIRQ
R/W
4
0
FF_E242H
2
C Controller waits until data is loaded. If this
R/W
2
TXI
Z16FMC Series Motor Control MCUs
C Controller after it sends the Start condi-
3
0
R/W1
NAK
2
0
I2C Master/Slave Controller
Product Specification
2
C Controller after a
FLUSH
2
R/W
C operation.
1
0
2
C Control-
FILTEN
R/W
0
0
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