Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 97

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Timer Control Register Definitions
Table 44. Timer 0–2 High Byte Register (TxH)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Reading Timer Count Values
Timer 0–2 High and Low Byte Registers
7
The current count value in the timer is read while counting (enabled). This has no effect on
timer operation. Normally, the count must be read with one 16-bit operation. However,
8-bit reads are performed using with the following method. When the timer is enabled and
the timer high byte register is read, the contents of the timer low byte register are placed in
a holding register. A subsequent read from the timer low byte register returns the value in
the holding register. This operation allows accurate reads of the full 16-bit timer count
value when enabled. When the timer is not enabled, a read from the timer low byte register
returns the actual value in the counter.
The Timers can be cascaded by using the Cascade bit in the Timer control registers. When
this bit is set for a Timer, the input source is redefined. When the Cascade bit is set for
Timer0, the input for Timer0 is the output of the Analog Comparator. When the Cascade
bit is set for Timer1 and Timer2, the output of Timer0 and Timer1 become the input for
Timer1 and Timer2, respectively. Any Timer Mode can be used. Timer0 can be cascaded
to Timer1 only by setting the Cascade bit for Timer1. Timer1 cascaded to Timer2 only by
setting the Cascade bit for Timer2. Or all three cascaded, Timer0 to Timer1 or Timer2 for
really long counts by setting the Cascade bit for Timer1 and Timer2.
The Timer 0–2 high and low byte (TxH and TxL) registers (see Tables 44 and 45) contain
the current 16-bit timer count value. When the timer is enabled, a read from TxH stores the
value in TxL to a temporary holding register. A read from TxL always returns this tempo-
rary register when the timer is enabled. When the timer is disabled, reads from the TxL
reads the register directly.
Writing to the timer high and low byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for Write operations, so
simultaneous 16-bit writes are not possible. When either of the timer high or low byte reg-
isters are written during counting, the 8-bit written value is placed in the counter (High or
Low Byte) at the next clock edge. The counter continues counting from the new value.
6
5
FF_E300H, FF_E310H, FF_E320H
P R E L I M I N A R Y
4
R/W
00H
TH
Z16FMC Series Motor Control MCUs
3
2
Product Specification
1
Timers
0
75