Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 234

Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D

Z16FMC32AG20EG

Manufacturer Part Number
Z16FMC32AG20EG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet

Specifications of Z16FMC32AG20EG

Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
- 40 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16FMC32AG20EG
Manufacturer:
Zilog
Quantity:
160
Part Number:
Z16FMC32AG20EG
Manufacturer:
Zilog
Quantity:
10 000
Table 114. Sample Time (ADCST)
Table 115. ADC Clock Prescale Register (ADCCP)
PS028702-1210
Bit Position
[7:4]
[3]
DIV16
[2]
DIV8
[1]
DIV4
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
Bit Position
[7:6]
[5:0]
SHT
ADC Clock Prescale Register
00H – 3FH
Value (H) Description
7
7
The ADC Clock Prescale register is used to provide a divided system clock to the ADC.
When this register is programmed with
Value (H) Description
Reserved
0H
0H
0
1
0
1
0
1
R
0
Reserved – Must be 0.
Sample Hold Time
Sample Hold time in number of system clock periods to meet 1 s minimum.
6
6
Reserved – must be 0.
DIV16
Clock is not divided.
System Clock is divided by 16 for ADC Clock.
DIV8
Clock is not divided.
System Clock is divided by 8 for ADC Clock.
DIV4
Clock is not divided.
System Clock is divided by 4 for ADC Clock.
Reserved
R
0
5
1
5
P R E L I M I N A R Y
4
1
4
FF_E505H
FF_E506H
0H
, the system clock is used for the ADC Clock.
DIV16
Z16FMC Series Motor Control MCUs
3
1
3
0
R/W
ST
DIV8
2
1
2
0
R/W
Product Specification
DIV4
1
1
1
0
Analog Functions
DIV2
0
1
0
0
212

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