Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 214

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
DMA Control of I
Note:
15. Software responds to the Stop interrupt by reading the I2CISTAT register, clearing the
The DMA engine is configured to support transmit and receive DMA requests from the
I
in the I
error condition interrupts to be handled by software while data movement is handled by
the DMA engine.
The DMA interface on the I
ter mode address byte transfer. The START, STOP and NAK bits must be controlled by
software.
A summary of I
Master Write Transaction with Data DMA
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The following procedure describes the I
10-bit addressing mode, transmitting data to the bus Master.

If the slave sends a Not Acknowledge prior to the final byte, a Not Acknowledge interrupt
2
C Controller. The I
SPRS
Configure the selected DMA channel for I
DMACTL register for the final buffer to be transferred.
The I
error conditions. A Not Acknowledge interrupt occurs on the final byte transferred.
The I
Master mode transactions. The
Initiate the I
page 178), using the
slave acknowledges.
Set the DMAIF bit in the I2CMODE register.
The DMA transfers the data, which is to be transmitted to the slave.
When the DMA interrupt occurs, poll the I2CSTAT register until the TDRE bit = 1.
This ensures that the I
byte written by the DMA.
Set the STOP bit in the I2CCTL register. The STOP bit is polled by software to deter-
mine when the transaction is actually completed.
Clear the DMAIF bit in the I2CMODE register.
2
C Mode Register and clearing the TXI bit in the I
2
2
bit.
C interrupt must be enabled in the interrupt controller to alert software of any I
C Master/Slave must be configured as defined in the sections above describing
2
C Transactions
2
2
C transfer of data using the DMA follows.
C transaction as described in the
2
C data interrupt requests must be disabled by setting the
ACKV
2
C Master/Slave hardware has commenced transmitting the final
P R E L I M I N A R Y
2
C Controller is intended to support data transfer but not mas-
and
ACK
TXI
2
bits in the I2CSTATE register to determine if the
bit in the I2CCTL register must be cleared.
C Master/Slave Controller operating as a Slave in
2
C transmit. The IEOB bit must be set in the
Z16FMC Series Motor Control MCUs
Master Address Only Transactions
2
C Control Register. This allows
I2C Master/Slave Controller
Product Specification
DMAIF
(see
bit
2
C
192