Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 186

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Bits
6,0
5
4
3
2
1
Description (Continued)
ESPIEN1, ESPIEN0 – ESPI Enable and Direction Control
00 = ESPI block is disabled. BRG is used as a general purpose timer by setting BRGCTL = 1.
01 = RECEIVE ONLY Mode.
Use this setting if the software application is receiving data but not sending. TDRE will assert,
however the transmit interrupt and DMA requests will not assert. In SLAVE mode, the transmit-
ted data will be all 1s. In MASTER mode software must still write to the Transmit Data Register
to initiate the transfer.
10 = TRANSMIT ONLY Mode
Use this setting in MASTER or SLAVE mode when the software application is sending data but
not receiving. RDRF will assert, but receive interrupt and DMA requests not occur.
11 = TRANSMIT/RECEIVE Mode
Use this setting if the software application is both sending and receiving information. Both
TDRE and RDRF will be active.
BRGCTL – Baud Rate Generator Control
The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows
enabling the BRG to provide periodic interrupts.
If the ESPI is disabled (ESPIEN1, ESPIEN0 = 00):
0 = The BRG timer function is disabled. Reading the Baud Rate High and Low registers returns
the BRG Reload value.
1 = The BRG timer function and timeout interrupt are enabled. Reading the Baud Rate High
and Low registers returns the BRG Counter value.
If the ESPI is enabled:
0 = Reading the Baud Rate High and Low registers returns the BRG Reload value. If MMEN = 1,
the BRG is enabled to generate SCK. If MMEN = 0, the BRG is disabled.
1 = Reading the Baud Rate High and Low registers returns the BRG Counter value. If MMEN =
1, the BRG is enabled to generate SCK. If MMEN = 0, the BRG is enabled to provide a Slave
SCK timeout. See Slave Abort error description.
CAUTION: If reading the counter one byte at a time while the BRG is counting keep in mind
that the values will not be in sync. It is recommended to read the counter using word (2-byte)
reads.
PHASE – Phase Select
Sets the phase relationship of the data to the clock. For more information about operation of
the PHASE bit, see the
CLKPOL – Clock Polarity
0 = SCK idles Low (0).
1 = SCK idles High (1).
WOR – Wire-OR (Open-Drain) Mode Enabled
0 = ESPI signal pins not configured for open-drain.
1 = All four ESPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain
MMEN – ESPI Master Mode Enable
This bit controls the data I/O pin selection and SCK direction.
0 = Data-out on MISO, data-in on MOSI (used in SPI Slave mode), SCK is an input.
1 = Data-out on MOSI, data-in on MISO (used in SPI Master mode), SCK is an output.
ESPI Clock Phase and Polarity Control
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
section on page 150.
Product Specification
164