Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 204

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Note:
Figure 36. Data Transfer Format – Master Read Transaction with 7-Bit Address
21. The I
If the Slave responds with a Not Acknowledge during the transfer, the I
asserts the NCKI bit, sets the
halts. Software terminates the transaction by setting either the STOP bit (end transaction)
or the START bit (end this transaction, start a new one). The transmit data register is
flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 36 displays the data transfer format for a read operation to a 7-bit addressed Slave.
Follow the procedure below to perform a Master read operation to a 7-bit addressed Slave.
1. Software initializes the MODE field in the I
2. Software writes the I
3. Software asserts the START bit of the I
4. If the operation is a single byte transfer, software asserts the NAK bit of the I
5. The I
6. The I
7. The I
8. The I
Slave Address
with 7- or 10-bit addressing (I
MODE field selects the address width for this node when addressed as a Slave, not for
the remote Slave. Software asserts the IEN bit in the I
Control Register so that after the first byte of data has been read by the I
a Not Acknowledge instruction is sent to the I
next High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. Software responds to the Not Acknowledge interrupt by setting the STOP bit
and clearing the TXI bit. The I
the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
signal.
2
2
2
2
2
C Controller sends the STOP condition to the I
C Controller sends the START condition.
C Controller sends the address and read bit out the SDA signal.
C Slave acknowledges the address by pulling the SDA signal Low during the
C Controller shifts in the first byte of data from the I
2
C Status Register, sets the
R=1
2
C Data Register with a 7-bit slave address plus the read bit (= 1).
P R E L I M I N A R Y
ACKV
A
2
2
C bus protocol allows mixing slave address types). The
bit and clears the
C Controller flushes the transmit data register, sends
ACKV
Data
2
C Control Register.
Z16FMC Series Motor Control MCUs
2
bit and clears the
C Mode Register for Master/Slave mode
2
C Slave.
ACK
A
2
bit in the I
2
C bus.
C Control Register.
2
C Controller sets the NCKI
I2C Master/Slave Controller
2
C Slave on the SDA
Product Specification
Data
ACK
2
C State Register and
bit in the I
2
C Controller
2
C Controller,
A
2
2
C
C State
P/S
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