Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 20

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Z16FMC Series Motor Control MCUs
Product Specification
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Table 101. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 102. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . 198
Table 103. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . 199
Table 104. I2C State Register (I2CSTATE) – Description when DIAG = 0 . . . . . . . 199
Table 105. I2C State Register (I2CSTATE) – Description when DIAG = 1 . . . . . . . 200
Table 106. I2CSTATE_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 107. I2CSTATE_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 108. I2C Mode Register (I2CMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 109. I2C Slave Address Register (I2CSLVAD) . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 110. ADC0 Control Register 0 (ADC0CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 111. ADC0 Data High Byte Register (ADC0D_H) . . . . . . . . . . . . . . . . . . . . . . 210
Table 112. ADC0 Data Low Bits Register (ADC0D_L) . . . . . . . . . . . . . . . . . . . . . . . 210
Table 113. Sample and Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 114. Sample Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 115. ADC Clock Prescale Register (ADCCP) . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 116. ADC0 MAX Register (ADC0MAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 117. ADC Timer0 Capture Register, high byte (ADCTCAP_H) . . . . . . . . . . . 213
Table 118. ADC Timer0 Capture Register, low byte (ADCTCAP_L) . . . . . . . . . . . . 214
Table 119. Comparator and Op Amp Control Register (CMPOPC) . . . . . . . . . . . . . . 216
Table 120. Linked list Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 121. DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 122. DMA Bandwidth Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 123. DMA Select Register (DMAxREQSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 124. DMA Control Register A (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 125. DMA X Transfer Length High Register (DMAxTXLNH) . . . . . . . . . . . . 237
Table 126. DMA X Transfer Length Low Register (DMAxTXLNL) . . . . . . . . . . . . . 237
Table 127. DMA X Destination Address Register Upper (DMAxDARU) . . . . . . . . . 237
Table 128. DMA X Destination Address Register High (DMAxDARH) . . . . . . . . . . 237
Table 129. DMA X Destination Address Register Low (DMAxDARL) . . . . . . . . . . 238
Table 130. DMA X Source Address Register Upper DMAxSARU . . . . . . . . . . . . . . 238
Table 131. DMA X Source Address Register High (DMAxSARH) . . . . . . . . . . . . . . 238
Table 132. DMA X Source Address Register Low (DMAxSARL) . . . . . . . . . . . . . . 238
Table 133. DMA X List Address Register Upper DMAxLARU . . . . . . . . . . . . . . . . 239
Table 134. DMA X List Address Register High (DMAxLARH) . . . . . . . . . . . . . . . . 239
Table 135. DMA X List Address Register Low (DMAxLARL) . . . . . . . . . . . . . . . . . 239
Table 136. Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
PS028702-1210
P R E L I M I N A R Y
List of Tables