Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 185

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 91. ESPI Control Register (ESPICTL)
PS028702-1210
Bits
7:2
1
0
Bits
Field
RESET
R/W
ADDR
Bits
7
ESPI Control Register
Description
Reserved
These bits are reserved.
TEOF – Transmit End Of Frame
This bit is used in Master mode to indicate that the data in the transmit data register is the final
byte of the transfer or frame. When the final byte has been sent SS (and SSV) change state
and TEOF automatically clears.
0 = The data in the transmit data register is not the final character in the message.
1 = The data in the transmit data register is the final character in the message.
SSV – Slave Select Value
When SSIO = 1, writes to this register controls the value output on the SS pin. See SSMD field
of the ESPI Mode Register for more details.
Description
DIRQE – Data Interrupt Request Enable
This bit is used to disable or enable data (TDRE and RDRF) interrupts. Disabling the data
interrupts is needed when controlling data transfer by DMA or polling. Error interrupts are not
disabled. To block all ESPI interrupt sources, clear the ESPI interrupt enable bit in the Interrupt
Controller.
0 = TDRE and RDRF assertions do not cause an interrupt.
RDRF. The TUND, COL, ABT and ROVR bits cause an interrupt.
1 = TDRE and RDRF assertions will cause an interrupt. TUND, COL, ABT and ROVR will also
cause interrupts. Use this setting if controlling data transfer through interrupt handlers.
Use this setting if controlling data transfer through DMA or by software polling of TDRE and
DIRQE
R/W
7
0
The ESPI Control Register (see Table 91) configures the ESPI for transmit and receive
operations.
ESPIEN1
R/W
6
0
BRGCTL
R/W
5
0
P R E L I M I N A R Y
PHASE
R/W
4
0
FF_E262H
CLKPOL
R/W
Z16FMC Series Motor Control MCUs
3
0
Enhanced Serial Peripheral Interface
WOR
R/W
2
0
Product Specification
MMEN
R/W
1
0
ESPIEN0
R/W
0
0
163