Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 77

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Table 31. Last IRQ Register (LASTIRQ)
Table 32. Interrupt Request 0 Register (IRQ0) and Interrupt Request 0 Set Register (IRQ0SET)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
Field
RESET
R/W
ADDR
Note: IRQ0SET at address FF_E031H is write only and used to set the interrupts identified.
Bits
7
6
Interrupt Request 0 Register
Description
T2I – Timer 2 Interrupt Request
0 = No interrupt request is pending for timer 2.
1 = An interrupt request from timer 2 is awaiting service. Writing a 1 to this bit resets it to 0.
T1I – Timer 1 Interrupt Request
0 = No interrupt request is pending for timer 1.
1 = An interrupt request from timer 1 is awaiting service. Writing a 1 to this bit resets it to 0.
Always 0
R/W1C
T2I
T2I
R
W
7
0
7
0
0
The Interrupt Request 0 (IRQ0) Register, shown in Table 32, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt con-
troller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the
CPU. If interrupts are globally disabled (polled interrupts), the CPU reads the Interrupt
Request 0 Register to determine if any interrupt requests are pending. Writing 1 to the bits
in this register clears the interrupt. The bits of this register are set by writing 1 to the inter-
rupt request 0 set regsiter (IRQ0SET) at address
R/W1C
R/W
T1I
T1I
W
6
0
6
0
0
R/W1C
R/W
T0I
T0I
W
5
0
5
0
0
P R E L I M I N A R Y
IRQADR
R/W1C
U0RXI
U0RXI
R/W
W
4
0
0
4
0
FF_E030H
FF_E031H
FF_E023H
R/W1C
U0TXI
U0TXI
R/W
Z16FMC Series Motor Control MCUs
W
3
0
0
3
0
FF_E031H
R/W1C
I2CI
I2CI
R/W
W
.
2
0
0
2
1
Product Specification
R/W1C
SPII
SPII
W
Interrupt Controller
1
0
0
R
1
0
Always 00
R/W1C
ADCI
ADCI
W
0
0
0
R
0
0
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