Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 249

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Linked List Mode
4. Write the DMAxTXLN with the transfer length.
5. Write DMAxLARU with water mark if required, otherwise write to zero.
6. Write DMAxCTL. Note that control register and address are directly written with
7. The DMA is now set up and begins operating when it receives a request.
After the DMA is set up and a request is received the DMA does the following:
1. Generate a request to the CPU.
2. It transfers data for each request until the transfer length reaches zero or the DMA
3. When the DMA receives the Request EOF signal, or the transfer length reaches zero it
Linked list mode requires the software to allocate buffers and set up a list of descriptors
for each buffer. After this allocation is performed, the software writes to DMAxLAR with
the address of the first descriptor. After the DMAxLAR is written, the DMA reads the first
descriptor into the DMA control and address registers with the exception of the LAR data.
It executes the transfers as specified by the descriptor data in the DMA. When the trans-
word and quad operations.
–
–
–
–
–
–
–
–
–
–
receives a Request EOF signal.
resets the
If
CMDSTAT field of the DMAxCTL register. If the
with a Request EOF the DMA channel generates a request to the CPU.
If
CPU.
EOF
EOF
DMAxEN; set to 1
LOOP; reset to 0, not used in this mode
TXSIZE; set to the transfer size, byte, word or quad
DSTCTL; set to fixed, increment, or decrement
SRCCTL; set to fixed, increment, or decrement
IEOB; set to 1 to generate an interrupt at the end of buffer or watermark
TXFR; reset to 0, not used in this mode
EOF; set this bit to one if it is an EOF buffer
HALT; reset to 0, not used in this mode
CMDSTAT; set these bits with the command for the peripheral
is set then the DMA reads the status from the peripheral and places it in the
is not set and
DMAxEN
bit and then does the following based upon the
IEOB
P R E L I M I N A R Y
is set then the DMA channel generates a request to the
Z16FMC Series Motor Control MCUs
IEOB
bit is set or the buffer ended
Product Specification
EOF
DMA Controller
and
IEOB
bits.
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