Z16FMC32AG20EG Zilog, Z16FMC32AG20EG Datasheet - Page 206

• Manufacturer Part Number: Z16FMC32AG20EG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
9. The I
10. The I
11. The I
12. Software responds by setting the
13. Software responds by writing
14. If you want to read only one byte, software responds by setting the
15. After the I
16. The I
17. The I
18. The I
19. The I
20. The I
21. The I
High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. Software responds to the Not Acknowledge interrupt by setting the STOP bit
and clearing the TXI bit. The I
the STOP condition on the bus and clears the
complete (ignore the following steps).
Register (lower byte of 10 bit address).
I
repeated Start.
(read) to the I
Control Register.
transfer), the I
the next High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. Software responds to the Not Acknowledge interrupt by setting the STOP bit
and clearing the TXI bit. The I
the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
Register (third address transfer).
Slave read address and a 1 (read).
High period of SCL.
2
C Controller generates a Transmit interrupt.
2
2
2
2
2
2
2
2
2
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller loads the I
C Controller shifts out the next eight bits of address. After the first bit shifts, the
C Controller sends the repeated START condition.
C Controller loads the I
C Controller sends
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller shifts in a byte of data from the Slave.
C Controller asserts the Receive interrupt.
2
2
2
C Controller shifts out the address bits mentioned in step 9 (second address
C Status Register, sets the ACKV bit and clears the
C Status Register, sets the
2
2
C Data Register.
C Slave sends an acknowledge by pulling the SDA signal Low during
P R E L I M I N A R Y
11110B
2
2
11110B
2
2
C Shift Register with the contents of the I
C Shift Register with the contents of the I
C Controller flushes the transmit data register, sends
C Controller flushes the transmit data register, sends
START
followed by the two most significant bits of the
ACKV
followed by the 2-bit slave address and a 1
bit of the I
Z16FMC Series Motor Control MCUs
bit and clears the
STOP
2
and
C Control Register to generate a
NCKI
2
2
C Controller sets the NCKI
C Controller sets the
I2C Master/Slave Controller
Product Specification
ACK
bits. The transaction is
ACK
bit in the I
bit in the I
NAK
bit of the I
2
2
C Data
C Data
2
2
C State
C State
NCKI
2
C
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