M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 105

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

The HEC coset is used to maintain a value other than zero in the HEC field. If the first four bytes in the header are
zero, the HEC derived from these bytes is also zero. When this occurs and there are strings of zeros in the data,
the receiver cannot determine cell boundaries. Therefore, it is recommended that the value 55 hex be added to the
HEC before transmission. To enable the HEC coset on the transmit side, set bit 6 in register CGEN (0x08) to one.
To enable the receive HEC coset, set bit 5 in register CVAL (0x0C) to one.
1.14.2
The ATM cell receiver performs cell delineation on incoming data cells by searching for the position of a valid HEC
field within the cell. The HEC coset can be either active or inactive; this is determined in bit 5 in the CVAL (0x0C)
register.
Figure 1-26. Details of the TC Block
1.14.2.1
The ATM block receives octets from the framers and recovers ATM cells by means of cell delineation. Cell
delineation is achieved by aligning ATM cell boundaries using the HEC algorithm. Four consecutive bytes are
chosen and the HEC value is calculated. The result is compared with the value of the following byte. This “hunt” is
continued by shifting this four-byte window, one byte at a time, until the calculated HEC value equals the received
HEC value. When this occurs, a pre-sync state is declared and the next 48 bytes are assumed to be payload. The
ATM block calculates HEC on the four bytes following this payload, assuming that a new cell has begun. If seven
28529-DSH-001-K
SPRxSync
SPTxSync
SPRxData
SPTxData
StatOut[0:1]
SPRxClkI
SPTxClk
Interface
Framer
(Line)
ATM Cell Receiver
This segment is replicated for Ports 0 - 7
Cell Delineation
Loopback
Control
Interrupt Control
TCK
TC Transmit Port
TC Receive Port
TRST*
JTAG Controller
MicroInt*
TMS
Mindspeed Proprietary and Confidential
Mindspeed Technologies
TDI
TDO
Alignment
Status and Control
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
MicroAddr[10:0]
8kHzIn
One Second Interface
®
Microprocessor
MicroData[7:0]
Interface
4-cell
FIFO
4-cell
FIFO
OneSecIO
Control Lines
Transmit
UTOPIA
UTOPIA
Receive
Level 2
Level 2
IMA
IMA
Functional Description
UTOPIA
Level 2
Interface
atmUTxClk
atmUTxClAv
atmUTxEnb*
atmUTxSOC
atmUTxData[15:0]
atmUTxPrty
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
atmURxSOC
atmURxData[15:0]
atmURxPrty
atmURxAddr[4:0]
500027_063
90