M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 200

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.3.15
2.3.16
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF10—TCCTRL0 (TC Control Register for TC ports 0-3)
0xF11—TCCTRL1 (TC Control Register for TC ports 4-7)
IhTxDatShft0
IhTxClkPol0
IhRxClkPol0
EnIH0
EnFrac[3]
EnFrac[2]
EnFrac[1]
EnFrac[0]
IhTxDatShft1
IhTxClkPol1
IhRxClkPol1
EnIH1
EnFrac[7]
EnFrac[6]
EnFrac[5]
EnFrac[4]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When set to 1, the Tx data on the Interleaved Highway Data Bus 0 will be output 1/2 IHTxClk0
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 0 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk0, set to 1 for
falling edge.
Interleaved Highway Bus 0 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk0, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 0-3.
When set, this bit enables fractional T1/E1 logic for TC port 3.
When set, this bit enables fractional T1/E1 logic for TC port 2.
When set, this bit enables fractional T1/E1 logic for TC port 1.
When set, this bit enables fractional T1/E1 logic for TC port 0.
When set to 1, the Tx data on the Interleaved Highway Data Bus 1 will be output 1/2 IHTxClk1
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 1 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk1, set to 1 for
falling edge.
Interleaved Highway Bus 1 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk1, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 4-7.
When set, this bit enables fractional T1/E1 logic for TC port 7.
When set, this bit enables fractional T1/E1 logic for TC port 6.
When set, this bit enables fractional T1/E1 logic for TC port 5.
When set, this bit enables fractional T1/E1 logic for TC port 4.
®
Description
Description
Registers
185