M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 37

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-9.
28529-DSH-001-K
MRdy
MicroClk
ExtMemSel
MemData[0]
MemData[1]
MemData[2]
MemData[3]
MemData[4]
MemData[5]
MemData[6]
MemData[7]
MemData[8]
MemData[9]
MemData[10]
MemData[11]
MemData[12]
MemData[13]
MemData[14]
MemData[15]
Pin Label
M28529 Pin Descriptions (3 of 19)
Microprocessor Ready
Microprocessor Clock
External Memory Enable
Differential Delay Memory
Data Bus
Signal Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
AC26
M26
No.
N24
N25
N26
P26
P25
P24
P23
R26
P22
R24
R23
U26
T26
T25
T24
R5
Y3
I/O/PD
I/PD
I/O
O
I
When active high, the current read or write transaction has been
completed. For a read transaction, the data is ready to be
transferred to the microprocessor. For a write transaction, the data
provided by the microprocessor has been written. This pin is an
open drain output for an external wired OR logic implementation.
An external pull-up resistor is required for this pin.
In asynchronous mode the microprocessor clock signal input can
be clocked up to 66 MHz. In synchronous mode this pin can be
clocked up to 25 MHz. The device samples the microprocessor
interface pins (MCS*, MW/R, MAS*, MicroAddr[11:0], and
Microdata[7:0]) on the rising edge of this signal. The
microprocessor interface output pins (Microdata[7:0], MicroInt*)
are clocked on the rising edge of MicroClk. Note that this clock is
required for both synchronous and asynchronous operations. See
note in
When this pin is pulled high, it enables the external differential
delay SRAM bus.
Differential delay SRAM Data Bus. ATM cells extracted from the
Receive data stream are stored in the SRAM for the purpose of
differential delay compensation.
This bus is enabled by pulling the ExtMemSel pin high.
®
Section
1.15.1.
Description
Functional Description
22