M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 170

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.6
The HDRFIELD register controls the header insertion elements.
2.2.7
The IDLPAY register contains the transmit idle cell payload.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0x09—HDRFIELD (Header Field Control Register)
0x0A—IDLPAY (Transmit Idle Cell Payload Control Register)
InsGFC
InsVPI
InsVCI
InsPT
InsCLP
IdlPay[7]
IdlPay[6]
IdlPay[5]
IdlPay[4]
IdlPay[3]
IdlPay[2]
IdlPay[1]
IdlPay[0]
Name
Name
—
—
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
When written to a logical 1, this bit inserts a Generic Flow Control (GFC) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the GFC field is not changed prior
to transmission.
When written to a logical 1, this bit inserts a Virtual Path Identifier (VPI) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the VPI field is not changed prior
to transmission.
When written to a logical 1, this bit inserts a Virtual Channel Identifier (VCI) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the VCI field is not changed prior
to transmission.
When written to a logical 1, this bit inserts a Payload Type (PT) field in the outgoing header from
the TXHDR registers. When written to a logical 0, the PT field is not changed prior to
transmission.
When written to a logical 1, this bit inserts a Cell Loss Priority (CLP) bit in the outgoing header
from the TXHDR registers. When written to a logical 0, the CLP field is not changed prior to
transmission.
These bits hold the Transmit Idle Cell Payload values for outgoing idle cells.
®
Description
Description
Registers
155