M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 181
M28529G-12
Manufacturer Part Number
M28529G-12
Description
ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529G-12.pdf
(309 pages)
Specifications of M28529G-12
Package
484BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3.135 V
Maximum Operating Supply Voltage
1.89|3.465 V
Maximum Output Rate
8.192 Mbps
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2.2.28
The RXMSK4 register contains the fourth byte of the Receive Cell Mask. (See 0x1D—RXMSK1.)
2.2.29
The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines ATM idle cells for the cell
receiver. Idle cells are discarded from the received stream if register CVAL (0x0C) bit 6 is set to 1. This header
consists of 32 bits divided among four registers.
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0x1F—RXMSK4 (Receive Cell Mask Control Register 4)
0x20—RXIDL1 (Receive Idle Cell Header Control Register 1)
RxMsk4[7]
RxMsk4[6]
RxMsk4[5]
RxMsk4[4]
RxMsk4[3]
RxMsk4[2]
RxMsk4[1]
RxMsk4[0]
RxIdl1[7]
RxIdl1[6]
RxIdl1[5]
RxIdl1[4]
RxIdl1[3]
RxIdl1[2]
RxIdl1[1]
RxIdl1[0]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
These bits hold the Receive Header Mask for Octet 4 of the incoming cell.
These bits hold the Receive Idle cell header for Octet 1 of the incoming cell.
®
Description
Description
Registers
166
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