M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 33

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Figure 1-7.
28529-DSH-001-K
Address Strobe, Write Control I
ATM Transmit Address Bus I
ATM Receive Address Bus I
Write/Read Read Control I
Sync/Async Mode Select I
External Memory Select I
Receive Data Marker I
Receive Data Marker I
ATM Transmit Enable I
IMA Reference Clock I
Microprocessor Clock I
PHY Interface Select I
ATM Receive Enable I
ATM Transmit Clock I
Memory Data Bus I/O
M28529 Logic Diagram (UTOPIA-to-Serial)
ATM Receive Clock I
IMA System Clock I
Test Mode Select I
Test Data Input I
Receive Clock I
Receive Clock I
Receive Data I
Receive Data I
8kHzIn Clock I
Address Bus I
Test Enable I
Chip Select I
Test Reset I
Test Clock I
Test Mode I
Reset I
MicroAddr[11:0]
SPRxData[0]
SPRxSync[0]
MCS
MAS*, MWr
MW/R, MRd
atmUTxAddr[4:0]
atmURxAddr[4:0]
SPRxClk[0]
PhyIntFcSel
MSyncMode
MicroClk
TRST
TDI
TestEnable
TestMode
atmUTxENB[1:0]
atmURxCLK
atmURxENB[1:0]
ExtMemSel
SPRxSync[31]
TCK
TMS
atmUTxCLK
IMA_SysClk
IMA_RefClk
8kHzin*
SPRxClk[31]
SPRxData[31]
MemData[15:0]
Reset*
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*
*
(1)
*
*
*
ATM UTOPIA Transmit
ATM UTOPIA Receive
Microprocessor
JTAG Interface
Line Interface
One Second
Line Interface
External Memory
Reset
Interface
Interface
IMA Clocks
Port 0
Port 31
Interface
Interface
Interface
(1)
Pulled High
atmUTxData[15:0]
atmURxData[15:0]
®
atmURxClAv[1:0]
MemCtrl_ADSC*
atmUTxClAv[1:0]
MemAddr[19:0]
MemCtrl_WE
MicroData[7:0]
MemCtrl_CE
MemCtrl_OE
MemCtrl_Clk
SPTxSync[31]
SPTxData[31]
atmUTxSOC
atmURxSOC
SPTxData[0]
SPTxSync[0]
StatOut [1:0]
SPTxClk[31]
atmUTxPrty
atmURxPrty
TxTRL[1:0]
SPTxClk[0]
OneSecIO
MicroInt
TDO
MRdy
*
*
*
*
O Transmit Data
I/O Transmit Data Marker
O ATM Receive Cell Available
O ATM Receive Start Of Cell
O ATM Receive Parity
O ATM Receive Data Bus
O Transmit Reference Clock
O Memory Address Bus
O Chip Enable
O Output Enable
O Write Enable
O SRAM Clock
O Address Enable
O Status Output
O Summary Interrupt
O Ready
I/O Microprocessor Data Bus
I/O Transmit Data Marker
I Transmit Clock
I/O One Second Input/Output
O Transmit Data
I Transmit Clock
O Test Data Output
O ATM Transmit Cell Available
I ATM Transmit Start Of Cell
I ATM Transmit Parity
I ATM Transmit Data Bus
Functional Description
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