M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 120
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M28529G-12
Manufacturer Part Number
M28529G-12
Description
ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529G-12.pdf
(309 pages)
Specifications of M28529G-12
Package
484BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3.135 V
Maximum Operating Supply Voltage
1.89|3.465 V
Maximum Output Rate
8.192 Mbps
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Figure 1-41. Interleaved Highway Mux
1.15
1.15.1
The microprocessor interface transfers control and status information in 8-bit data transfers between the external
microprocessor and M2852x by means of write and/or read access to internal registers. This interface allows the
microprocessor to configure the M2852x by writing various control registers. These control registers can also be
read for configuration confirmation. This interface also provides the ability to read the device’s current condition via
its status registers and counters. Summary status is available for rapid interrupt identification.
The microprocessor interface can operate in either an asynchronous mode or a synchronous mode. The
MSyncMode (pin AE24) determines which mode is active.
In the synchronous mode, the timing of these signals is synchronized to MicroClk, which is intended to be directly
driven by the external microprocessor.
1.15.1.1
There are four software controlled reset functions, two at the device level and two at the port level. The two levels
allow a user to reset either the entire M2852x with one command or only a port within the device. The two logic
resets allow the user to keep the device or port in a reset state while the control registers are being programmed.
When the reset bit is deasserted, all changes to the registers take place simultaneously.
28529-DSH-001-K
NOTE:
General Issues
Micro Interface
Resets
Interleaved Highway Group
The MicroClk is required for both modes. In asynchronous mode, a MicroClk frequency of
up to 66MHz, must be present but can be asynchronous to the other microprocessor
signals. In synchronous mode, MicroClk is limited to 25MHz.
processor
processor
processor
processor
TC cell
TC cell
TC cell
TC cell
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Line interface
Line interface
Line interface
Line interface
n+1
n+2
n+3
n
®
4 x 1
Mux
Functional Description
105
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