M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 108

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-26.
1.14.2.3
The M2852x provides two optional types of cell screening. The first type, idle cell rejection, prevents idle cells from
being passed on. The second type, user traffic screening, compares incoming bits to the values in the receive cell
header registers. Cells are rejected or accepted based on the bit patterns of their headers.
Idle cell rejection is enabled in bit 6 of the CVAL register (0x0C). If this bit is set to 1, all incoming cells that match
the contents of the Receive Idle Cell Header Control Registers, RXIDL1–4 (0x20–23), are rejected. Individual bits
in the Receive Idle Cell Mask Control Registers, IDLMSK1–4 (0x24–27), can be set to 1 or Don’t Care, causing the
corresponding bits of the incoming cell to be treated as matching, regardless of their value. If idle cell rejection is
disabled, cells pass directly to user traffic screening.
User traffic cell screening is similar to idle cell screening in that the incoming cells are compared to the Receive
Cell Header Control Registers, RXHDR1–4 (0x18–1B). Individual bits in the Receive Cell Mask Control Registers,
RXMSK1–4 (0x1C–1F), can be set to 1 or Don’t Care, causing the corresponding bits of the incoming cell to be
treated as matching, regardless of their values. The RejHdr bit (bit 7) in the CVAL register (0x0C) determines
whether matching cells are rejected or accepted. If it is set to 0, matching cells are accepted. If it is set to 1,
matching cells are rejected. See
28529-DSH-001-K
General Note:
1. The HEC Error Correction circuit is independent of the DisHECChk control bit. The M28529 will correct single bit errors even when the
DisLOCD
DisHECChk is enabled (assuming that the EnHECCor bit is set to 1).
0
0
1
1
Control Bit Functions
DisHECChk
Cell Screening
0
1
0
1
Normal operation; used for standard ATM traffic.
Cells are output to the UTOPIA FIFO only after cell delineation is found. Only cells with valid HECs are
passed (this includes cells with single bit errors that have been corrected).
Ignore HEC Errors Mode; used for IMA applications.
The Cell Delineator state machine is active and looking for valid ATM cells. It will follow the ATM Forum’s
Cell Delineation process. However, since the Cell Valid State machine is turned off, the M28529 will pass
all cells, including those with HEC errors, to the UTOPIA FIFOs.
The M28529 will not transfer cells during LOCD.
The cell delineation function is disabled and every 53 bytes of incoming data is treated as a ‘cell’. How-
ever, since the CV machine is still active, only cells with valid HECs will be output. As a result, almost all
data will be dropped. Occasionally, random data will have what appears to be a valid HEC and will be out-
put. Mindspeed is not aware of any use for this mode.
Raw Data mode; allows the M28529 to be used as a generic ‘serial to parallel’ convertor.
All data received will be passed across the UTOPIA bus in blocks of 53 bytes. No attempt is made to find
ATM cells.
Table 1-27
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and
Table
1-28.
Description
®
Functional Description
93