M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 168

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.4
The IOMODE register controls the line interface signal polarities and status outputs.
28529-DSH-001-K
Footnote:
(1) These bits should only be changed when the device or port logic reset is asserted.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x05—IOMODE (Input/Output Mode Control Register)
RxSyncPol
RxClkPol
TxSyncPol
TxClkPol
TxDatShft
(1)
Name
(1)
(1)
(1)
(1)
—
—
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Reserved, set to 0.
This bit determines the Receiver Synchronization input Polarity. When written to a logical 1, the
active level on the SPRxSync input is high. When written to a logical 0, the active level is low.
This bit determines the Receiver Clock Input Polarity. When written to a logical 1, the active edge
on the SPRxClk input is the falling edge. When written to a logical 0, the active edge is the rising
edge.
This bit determines the Transmitter Synchronization input Polarity. When written to a logical 1,
the active level on the SPTxSync input is high. When written to a logical 0, the active level is low.
This bit determines the Transmitter Clock Input Polarity. When written to a logical 1, the active
edge on the SPTxClk input is the falling edge. When written to a logical 0, the active edge is the
rising edge.
This bit when set to a logical 1 shifts the serial Tx data by 1/2 a cycle. This results in the Tx data
being output a 1/2 SPTxClk cycle later than when the Tx inputs are sampled. This feature is
disabled when set to 0.
Reserved, set to 0.
Reserved, set to 0.
®
Description
Registers
153