M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 85

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

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•
It should be noted that the IMA frame rates can not be directly derived from the SPTxClk[31:0] inputs.
In a typical application (see Case 1 in
the Rx direction is slaved to the FE Tx. It is also quite common (Case 2 in
slaved to the FE Tx, often using the same source as the Rx direction. In some rarer applications, (Case 3 in
Table
Table 1-18.
Internally the IMA engine generates a Transmit Data Cell Rate clock (Tx IDCR) to match the exact cell rate of each
group in the transmit side of the IMA device. The IMA engine also generates a Receive Data Cell Rate clock (Rx
IDCR) to match receive cell rate for each group and operates the Receive Cell Smoothing buffer. There is a Tx
IDCR and Rx IDCR for each of the 32 groups that the M28529 supports.
The M28529 also provides two clock outputs: Tx_TRL[1] and Tx_TRL[0]. These can be used to output one of the
reference clock inputs or generate an 8 KHz reference that is phase locked to IMA_SysClk or IMA_RefClk
(whichever is used as a timing reference).
Figure 1-16
generating all clocks required by the IMA engine. It can be further divided into 8 sections, as shown in
28529-DSH-001-K
Footnotes:
(1) These sources provide a “last resort” clock in case no valid timing can be derived from Rx side sources.
(2) This case assumes the FE Tx is loop timed to the NE Tx; this will limit applications. It is also applicable in loopback testing.
Case
3
1
2
•
•
SPRxClk or IHRxClk
•
Rx PHY side cell stream
•
(2)
1-18) both the Tx and Rx directions are referenced from local clock sources.
Line rate clock input or
Programmable divider
PHY Line/Payload rate clock
PHY payload rate derived (synthesized) from cell transfer rate across PHY side UTOPIA interface
shows the details of the M28529's IMA clock block from
Master / Internal
Master / Internal
Configuration
Slave / External
Reference Clock Configurations / Sources
Tx Direction
IMA_SysClk or IMA_RefClk
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Table
Possible Sources
SPRxClk or IHRxClk
Rx Cell stream
IMA_SysClk
IMA_SysClk
IMA_RefClk
IMA_RefClk
1-18), the Tx direction is referenced from local clock sources whereas
Master / Internal
Configuration
Slave / External
Slave / External
®
Figure
Table
1-1. This block is responsible for
1-18) for the Tx direction to be
Rx Direction
Functional Description
IMA_SysClk or IMA_RefClk
IMA_SysClk or IMA_RefClk
SPRxClk or IHRxClk
SPRxClk or IHRxClk
Rx Cell stream
Rx Cell stream
IMA_SysClk
IMA_RefClk
Sources
Table
1-19:
(1)
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